AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 151

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.3.3.6
6257A–ATARM–20-Feb-08
Security Bit Protection
One error can be detected in the MC_FSR register after a programming sequence:
It is possible to clear GPNVM bits previously set. The clear GPNVM bit sequence is:
One error can be detected in the MC_FSR register after a programming sequence:
The status of GPNVM bits can be returned by the Enhanced Embedded Flash Controller
(EEFC). The sequence is:
For example, if the third bit of the first word read in the MC_FRR is set, then the third GPNVM bit
is active.
One error can be detected in the MC_FSR register after a programming sequence:
Note:
When the security is enabled, access to the Flash, either through the ICE interface or through
the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code
programmed in the Flash.
The security bit is GPNVM0.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full
Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are
permitted.
• When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register
• If the GPNVM bit number is greater than the total number of GPNVM bits, then the command
• A Command Error: a bad keyword has been written in the MC_FCR register.
• Start the Clear GPNVM Bit command (CGPB) by writing the Flash Command Register with
• When the clear completes, the bit FRDY in the Flash Programming Status Register
• If the GPNVM bit number is greater than the total number of GPNVM bits, then the command
• A Command Error: a bad keyword has been written in the MC_FCR register.
• Start the Get GPNVM bit command by writing the Flash Command Register with GGPB. The
• When the command completes, the bit FRDY in the Flash Programming Status Register
• GPNVM bits can be read by the software application in the MC_FRR register. The first word
• a Command Error: a bad keyword has been written in the MC_FCR register.
(MC_FSR) rises. If an interrupt was enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
has no effect. The result of the SGPB command can be checked by running a GGPB (Get
GPNVM Bit) command.
CGPB and the number of the GPNVM bit to be cleared.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
has no effect.
FARG field is meaningless.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM
bits as long as it is meaningful. Extra reads to the MC_FRR register return 0.
Access to the Flash in read is permitted when a set, clear or get GPNVM bit command is
performed.
AT91SAM7L128/64 Preliminary
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