AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 48
![MCU ARM7 64K HS FLASH 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7L64-AU
Manufacturer Part Number
AT91SAM7L64-AU
Description
MCU ARM7 64K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7L64-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Controller Family/series
AT91SAM7xxx
No. Of I/o's
80
Ram Memory Size
6KB
Cpu Speed
36MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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11.2.4.2
11.2.4.3
11.2.5
48
AT91SAM7L128/64 Preliminary
ARM Instruction Set Overview
Status Registers
Exception Types
A seventh processing mode, System Mode, does not have any banked registers. It uses the
User Mode registers. System Mode runs tasks that require a privileged processor mode and
allows them to invoke all classes of exceptions.
All other processor states are held in status registers. The current operating processor status is
in the Current Program Status Register (CPSR). The CPSR holds:
All five exception modes also have a Saved Program Status Register (SPSR) that holds the
CPSR of the task immediately preceding the exception.
The ARM7TDMI
The types of exceptions are:
Exceptions are generated by internal and external sources.
More than one exception can occur in the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save state.
To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to
the PC. This can be done in two ways:
The ARM instruction set is divided into:
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bit[31:28]).
• four ALU flags (Negative, Zero, Carry, and Overflow)
• two interrupt disable bits (one for each type of interrupt)
• one bit to indicate ARM or Thumb execution
• five bits to encode the current processor mode
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupts (SWIs)
• by using a data-processing instruction with the S-bit set, and the PC as the destination
• by using the Load Multiple with Restore CPSR instruction (LDM)
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
supports five types of exception and a privileged processing mode for each type.
6257A–ATARM–20-Feb-08
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