UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 637

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

26.2 Operation List
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
8-bit data
transfer
Instruction
Group
2.
3.
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
MOV
XCH
Mnemonic
register (PCC).
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 26 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U17554EJ4V0UD
Bytes
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
3
1
1
2
2
2
Note 1
4
6
−
2
2
4
4
−
−
8
8
−
−
−
4
4
4
4
8
8
6
6
6
6
2
4
−
8
4
4
8
8
8
Clocks
Note 2
10
10
10
10
7
5
9
5
5
7
7
−
7
−
−
5
5
5
9
7
5
5
5
5
9
9
7
7
−
6
6
6
6
r ← byte
(saddr) ← byte
sfr ← byte
A ← r
r ← A
A ← (saddr)
(saddr) ← A
A ← sfr
sfr ← A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
(HL) ← A
A ← (HL + byte)
(HL + byte) ← A
A ← (HL + B)
(HL + B) ← A
A ← (HL + C)
(HL + C) ← A
A ↔ r
A ↔ (saddr)
A ↔ (sfr)
A ↔ (addr16)
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A ↔ (HL + B)
A ↔ (HL + C)
CPU
) selected by the processor clock control
Operation
Z AC CY
×
×
Flag
×
×
637
×
×