UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 572

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

21.2 Configuration of Power-on-Clear Circuit
21.3 Operation of Power-on-Clear Circuit
(1) In 1.59 V POC mode (option byte: LVISTART = 0)
(2) In 2.7 V/1.59 V POC mode (option byte: LVISTART = 1)
572
The block diagram of the power-on-clear circuit is shown in Figure 21-1.
• An internal reset signal is generated on power application. When the supply voltage (V
• The supply voltage (V
• An internal reset signal is generated on power application. When the supply voltage (V
• The supply voltage (V
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is
shown below.
detection voltage (V
internal reset signal is generated. It is released when V
detection voltage (V
internal reset signal is generated. It is released when V
V
DD
POC
DDPOC
DD
DD
Figure 21-1. Block Diagram of Power-on-Clear Circuit
= 1.59 V ±0.15 V), the reset status is released.
) and detection voltage (V
) and detection voltage (V
= 2.7 V ±0.2 V), the reset status is released.
Reference
voltage
source
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
User’s Manual U17554EJ4V0UD
+
V
DD
POC
POC
= 1.59 V ±0.15 V) are compared. When V
= 1.59 V ±0.15 V) are compared. When V
DD
DD
≥ V
≥ V
POC
DDPOC
.
.
Internal reset signal
DD
DD
) exceeds the
) exceeds the
DD
DD
< V
< V
POC
POC
, the
, the