UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 156

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(8) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
156
Status Transition
(C) → (B)
Status Transition
(C) → (D) (XT1 clock)
(C) → (D) (external subsystem clock)
Status Transition
(D) → (C) (X1 clock: less than 10 MHz)
(D) → (C) (external main clock: less than
10 MHz)
(D) → (C) (X1 clock: 10 MHz or more)
(D) → (C) (external main clock: 10 MHz or
more)
Remarks 1. (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-14.
(Setting sequence of SFR registers)
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
MSTOP:
XSEL, MCM0:
CSS:
RSTS, RSTOP: Bits 7 and 0 of the internal oscillator mode register (RCM)
Table 6-4. CPU Clock Transition and SFR Register Setting Examples (3/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
Unnecessary if these registers
CHAPTER 6 CLOCK GENERATOR
AMPH
0
0
1
1
User’s Manual U17554EJ4V0UD
are already set
with the internal high-speed oscillation clock
EXCLK
EXCLKS
0
1
0
1
Unnecessary if the CPU is operating
RSTOP
0
1
Unnecessary if the CPU is operating
0
OSCSEL
with the subsystem clock
1
1
1
1
OSCSELS
with the high-speed
MSTOP
Unnecessary if the
CPU is operating
Confirm this flag is 1.
1
1
system clock
0
0
0
0
Must not be
Must not be
RSTS
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
Unnecessary if this register is
XSEL
1
1
1
1
↑
already set
MCM0
1
1
1
1
MCM0
0
CSS
1
1
CSS
0
0
0
0