UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 335

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

14.4 Operations of Serial Interface UART60 and UART61
14.4.1 Operation stop mode
addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and
5 (POWER6n, TXE6n, and RXE6n) of ASIM6n to 0.
(1) Register used
Address: FF50H After reset: 01H R/W
ASIM6n
Serial interfaces UART60 and UART61 have the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In
Notes 1.
Caution Clear POWER6n to 0 after clearing TXE6n and RXE6n to 0 to stop the operation.
Remarks 1. To use the RxD60/P14, RxD61/P11/SI10, TxD60/P13 and TxD61/P10/SCK10 pins as general-
Symbol
The operation stop mode is set by asynchronous serial interface operation mode register 6n (ASIM6n).
ASIM6n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
2.
2. n = 0, 1
To start the communication, set POWER6n to 1, and then set TXE6n and RXE6n to 1.
POWER6n
POWER6n
The output of the T
POWER6n = 0.
Asynchronous serial interface reception error status register 6n (ASIS6n), asynchronous serial
interface transmission status register 6n (ASIF6n), bit 7 (SBRF6n) and bit 6 (SBRT6n) of asynchronous
serial interface control register 6n (ASICL6n), and receive buffer register 6n (RXB6n) are reset.
RXE6n
TXE6n
purpose port pins, see CHAPTER 5 PORT FUNCTIONS.
0
<7>
Note 1
0
0
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Disables transmission operation (synchronously resets the transmission circuit).
Disables reception (synchronously resets the reception circuit).
TXE6n
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
<6>
X
D6n pins goes high and the input from the R
RXE6n
<5>
User’s Manual U17554EJ4V0UD
Enables/disables operation of internal operation clock
Note 2
.
PS61n
4
Enables/disables transmission
Enables/disables reception
PS60n
3
X
CL6n
D6n pins is fixed to high level when
2
SL6n
1
ISRM6n
0
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