UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 219
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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(4) Timing of holding data by capture register
(5) Setting valid edge
(6) Re-triggering one-shot pulse
(a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while
(b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops.
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the
valid edge by using ES0n0 and ES0n1.
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
Remark n = 0 to 3
CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not
guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the
TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI00n
pin is detected).
When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the
value of CR00n/CR01n after INTTM00n/INTTM01n is generated.
Value captured to CR01n
Capture read signal
TM0n count value
Count pulse
Edge input
INTTM01n
Figure 7-56. Timing of Holding Data by Capture Register
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
X
Capture operation
N
User’s Manual U17554EJ4V0UD
N + 1
N + 2
N + 1
M
Capture operation is performed
but read value is not guaranteed.
M + 1
M + 2
219
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