UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet
UPD78F0890GK(A)-GAJ-AX
Specifications of UPD78F0890GK(A)-GAJ-AX
Related parts for UPD78F0890GK(A)-GAJ-AX
UPD78F0890GK(A)-GAJ-AX Summary of contents
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... Do not use this product for mass production after the on-chip debug function has been used because its reliability cannot be guaranteed, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning when use this product for mass production after the on-chip debug function has been used ...
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User’s Manual U17554EJ4V0UD ...
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... IH HANDLING OF UNUSED INPUT PINS 2 Unconnected CMOS device inputs can be cause of malfunction input pin is unconnected possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V via a resistor if there is a possibility that it will be an output pin ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others ...
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User’s Manual U17554EJ4V0UD 5 ...
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Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/FE2 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/FE2: Purpose This manual is intended ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing ...
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... DD DD 2.2.17 V and EV ................................................................................................................................... 2.2.18 FLMD0 ............................................................................................................................................ 36 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 37 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 41 3.1 Memory Space .............................................................................................................................. 41 3.1.1 Internal program memory space........................................................................................................ 48 μ 3.1.2 Bank area ( PD78F0889 and 78F0890 only).................................................................................... 49 3.1.3 Internal data memory space .............................................................................................................. 51 3.1.4 Special function register (SFR) area ................................................................................................. 51 3 ...
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Relative addressing............................................................................................................................68 3.3.2 Immediate addressing........................................................................................................................69 3.3.3 Table indirect addressing ...................................................................................................................70 3.3.4 Register addressing ...........................................................................................................................70 3.4 Operand Address Addressing .................................................................................................... 71 3.4.1 Implied addressing .............................................................................................................................71 3.4.2 Register addressing ...........................................................................................................................72 3.4.3 Direct addressing ...............................................................................................................................73 3.4.4 Short direct addressing ......................................................................................................................74 3.4.5 Special ...
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Configuration of Clock Generator ............................................................................................ 126 6.3 Registers Controlling Clock Generator.................................................................................... 128 6.4 System Clock Oscillator ............................................................................................................ 137 6.4.1 X1 oscillator......................................................................................................................................137 6.4.2 XT1 oscillator....................................................................................................................................137 6.4.3 When subsystem clock is not used ..................................................................................................140 6.4.4 Internal high-speed oscillator............................................................................................................140 6.4.5 Internal low-speed ...
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CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 240 9.1 Functions of 8-Bit Timers H0 and H1 ....................................................................................... 240 9.2 Configuration of 8-Bit Timers H0 and H1................................................................................. 240 9.3 Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 244 9.4 Operation ...
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... CAN sleep mode/CAN stop mode function ....................................................................................392 16.3.6 Error control function ......................................................................................................................393 16.3.7 Baud rate control function ..............................................................................................................399 16.4 Connection with Target System.............................................................................................. 403 16.5 Internal Registers of CAN Controller...................................................................................... 404 16.5.1 CAN controller configuration...........................................................................................................404 16.5.2 Register access type ......................................................................................................................405 16 ...
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Message reception.........................................................................................................................458 16.9.2 Receive Data Read ........................................................................................................................459 16.9.3 Receive history list function............................................................................................................460 16.9.4 Mask function .................................................................................................................................462 16.9.5 Multi buffer receive block function ..................................................................................................464 16.9.6 Remote frame reception.................................................................................................................465 16.10 Message Transmission.......................................................................................................... 466 16.10.1 Message transmission .................................................................................................................466 16.10.2 Transmit history list ...
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... Internal Expansion RAM Size Switching Register ................................................................ 601 24.3 Writing with Flash Memory Programmer ............................................................................... 602 24.4 Programming Environment ..................................................................................................... 605 24.5 Communication Mode.............................................................................................................. 605 24.6 Connection of Pins on Board.................................................................................................. 607 24.6.1 FLMD0 pin......................................................................................................................................607 24.6.2 Serial interface pins........................................................................................................................607 24.6.3 RESET pin......................................................................................................................................609 24 ...
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... Boot Swap Function .............................................................................................................. 628 CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................................................................................... 630 25.1 Outline of Functions ................................................................................................................ 630 25.2 Connection with MINICUBE .................................................................................................... 631 25.3 Connection Circuit Examples ................................................................................................. 632 25.4 On-Chip Debug Security ID ..................................................................................................... 634 25.5 Restrictions and Cautions on On-Chip Debug Function ..................................................... 634 CHAPTER 26 INSTRUCTION SET ...................................................................................................... 635 26 ...
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APPENDIX A DEVELOPMENT TOOLS............................................................................................... 700 A.1 Software Package ...................................................................................................................... 704 A.2 Language Processing Software ............................................................................................... 704 A.3 Control Software ........................................................................................................................ 705 A.4 Flash Memory Programming Tools.......................................................................................... 706 A.4.1 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3 ......................706 A.4.2 ...
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... On-chip watchdog timer (operable with on-chip internal low-speed oscillator clock) On-chip multiplier/divider On-chip clock output/buzzer output controller I/O ports: 55 (N-ch open drain: 4) Timer: 10 channels Serial interface: 4 channels (UART (LIN (Local Interconnect Network)-bus supported): 1 channel, Note CSI/UART : 1 channel, CSI: 1 channel, CAN: 1 channel) 10-bit resolution A/D converter: 12 channels Supply voltage ...
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Applications Automotive electrical appliances (Body control, Door control, Front light control) Industrial equipment (Industrial robot, Building control) 1.3 Ordering Information • Flash memory version Part Number μ PD78F0887GK(A)-GAJ-AX 64-pin plastic LQFP (12x12) μ PD78F0887GK(A2)-GAJ-AX 64-pin plastic LQFP (12x12) μ ...
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... P122/X2/EXCLK 10 P121/X1 11 REGC Cautions 1. Make AV and Make EV the same potential Connect the REGC pin ANI0/P80 to ANI11/P93 are set in the analog input mode after release of reset. CHAPTER 1 OUTLINE the same potential via a capacitor (0. User’s Manual U17554EJ4V0UD REF 46 P10/SCK10/TxD61 45 P11/SI10/RxD61 44 P12/SO10 43 P13/TxD60 ...
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Pin Identification ANI0 to ANI11: Analog input AV : Analog reference voltage REF AV : Analog ground SS BUZ: Buzzer output CRxD: Receive data for CAN CTxD: Transmit data for CAN EV : Power supply for port ...
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Fx2 Series Lineup 1.5.1 78K0/Fx2 product lineup 44-pin LQFP ( 0.8 mm pitch) 78K0/FC2 PD78F0881 PD78F0882 Single-power-supply flash Single-power-supply flash memory: 32 KB, memory: 48 KB, RAM RAM 48-pin LQFP ( ...
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The list of functions in the 78K0/Fx2 is shown below. Part Number Item Number of pins Internal Flash memory memory RAM (bytes) Power supply voltage Minimum instruction execution time Clock Crystal/ceramic Subclock Internal low-speed oscillator Internal high-speed oscillator Ports CMOS ...
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Block Diagram TO00/TI010/P01 16-bit timer/ event counter 00 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) TO01/TI011/P06 16-bit timer/ event counter 01 TI001/P05 TO02/TI012/P32 16-bit timer/ event counter 02 TI002/P31 TO03/TI013/P132 16-bit timer/ event counter 03 TI003/P131 TOH0/P15 8-bit timer H0 TOH1/P16 8-bit ...
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Outline of Functions μ Item Internal Flash memory memory (self-programming Note (bytes) supported) Bank Note High-speed RAM Note Expansion RAM Memory space High-speed system clock Crystal/ceramic oscillation (X (oscillation frequency MHz MHz: ...
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Item CAN Serial interface 3-wire CSI LIN-UART LIN-UART/ Note CSI Multiplier/divider <R> Vectored Internal interrupt sources External Reset On-chip debug function Supply voltage Operating ambient temperature Package Note Select either of the functions of these alternate-function pins. An outline of ...
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Pin Function List There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply AV REF This section explains the names and functions of the ...
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Pin Name I/O P50 to P53 I/O Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 to P63 I/O Port 6. 4-bit I/O ...
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Non-port pins Pin Name I/O INTP0 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be INTP1 specified INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 SI10 Input Serial ...
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... EV Ground potential for ports SS − FLMD0 Flash memory programming mode setting. − REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin CHAPTER 2 PIN FUNCTIONS Table 2-3. Non-port pins (2/2) Function . SS via a capacitor (0. µF: recommended). ...
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Description of Pin Functions 2.2.1 P00, P01, P05, P06 (port 0) P00, P01, P05 and P06 function as a 4-bit I/O port. These pins also function as timer I/O and serial interface chip select input. The following operation modes ...
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P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can ...
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... Cautions 1. Be sure to pull the P31/TI002/INTP2 pin down before a reset release, to prevent malfunction. 2. Connect P31/TI002/INTP2 as follows when writing the flash memory with a flash programmer. - P31/TI002/INTP2: Connect to EV The above connection is not necessary when writing the flash memory by means of self programming. Remark P31/TI002/INTP2 and P32/TI012/TO02/INTP3 can be used as on-chip debug mode setting pins when the on-chip debug function is used ...
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P50 to P53 (port 5) P50 to P53 function as a 4-bit I/O port. P50 to P53 can be set to input or output in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor ...
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... Control mode P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage detection, resonator connection for main system clock, resonator connection for subsystem clock, external clock input for main system clock and external clock input for subsystem clock. ...
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... P121/X1: When using this pin as a port, connect recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Remark The X1 and X2 pins can be used as on-chip debug mode setting pins when the on-chip debug function is used ...
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... SS 2.2.14 RESET This is the active-low system reset input pin. 2.2.15 REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin to V via a capacitor (0. µF: recommended). SS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. ...
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... Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-4 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Pin Name P00/TI000 P01/TI010/TO00 P05/SSI11/TI001 P06/TI011/TO01 P10/SCK10/TxD61 ...
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... FLMD0 Notes 1. P80/ANI0 to P87/ANI7 and P90/ANI8 to P93/ANI11 are set in the analog input mode after release of reset. 2. Use the recommended connection above in I/O port mode (see Figure 6-6 Format of Clock Operation Mode Select Register (OSCCTL)) when these pins are not used. 3. Connect P121/X1 as follows when writing the flash memory with a flash programmer. ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 3-C EV P-ch Data N-ch Vss0 Type 5-AH Pull-up enable EV DD Data P-ch Output N-ch disable EV SS Input enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List ...
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Type Reset Data P-ch Output N-ch disable EV SS Input enable EV DD Reset Data P-ch Output N-ch disable EV SS Input enable 40 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) X2, XT2 ...
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Memory Space Products in the 78K0/FE2 can each access memory space. Figures 3-1 to 3-4 show the memory map. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register ...
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FFFFH Special function registers (SFR) 256 FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 Note 1 FB00H FAFFH AFCAN area (256 FA00H F9FFH Data memory Reserved space F800H F7FFH RAM space in Internal expansion RAM ...
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FFFFH Special function registers (SFR) 256 8 bits FF00H FEFFH General-purpose registers FEE0H 32 8 bits FEDFH Internal high-speed RAM 1024 Note 1 FB00H FAFFH AFCAN area (256 8 bits) FA00H F9FFH Data memory Reserved space F800H F7FFH RAM space ...
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FFFFH Special function registers (SFR) FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH AFCAN area FA00H F9FFH Data memory space F800H F7FFH RAM space in Internal expansion RAM which ...
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Figure 3-4. Memory Map ( FFFFH Special function registers (SFR) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits Note 1 FB00H FAFFH AFCAN area 256 × 8 ...
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Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2) μ (1) PD78F0887, 78F0888 Block Address Value Address Value Number 0000H to ...
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Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2) μ (2) PD78F0889, 78F0890 Address Value Block Address Value Number 0000H to 03FFH 00H 8000H to 83FFH 0400H to 07FFH 01H 8400H to 87FFH 0800H to 0BFFH ...
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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). 78K0/FE2 products incorporate internal ROM (flash memory), as shown below. Part Number Structure μ PD78F0887 ...
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CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The option byte area is assigned to the 1-byte area of 0080H. Refer ...
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PD78F0890 Bank area 0 16384 8 bits The following table shows the relations among bank numbers, CPU addresses, ...
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Internal data memory space 78K0/FE2 products incorporate the following RAM. (1) Internal high-speed RAM Table 3-6. Internal High-Speed RAM Capacity Part Number μ PD78F0887 μ PD78F0888 μ PD78F0889 μ PD78F0890 The 32-byte area FEE0H to FEFFH is assigned to ...
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Figure 3-6. Correspondence Between Data Memory and Addressing ( FFFFH Special function registers (SFR) 256 8 bits FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits Note 1 FB00H FAFFH AFCAN area (256 8 ...
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Figure 3-7. Correspondence Between Data Memory and Addressing ( FFFFH Special function registers (SFR) 256 8 bits FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits Note 1 FB00H FAFFH AFCAN area (256 8 ...
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Figure 3-8. Correspondence Between Data Memory and Addressing ( FFFFH Special function registers (SFR) 256 8 bits FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits Note 1 FB00H FAFFH AFCAN area (256 8 ...
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Figure 3-9. Correspondence Between Data Memory and Addressing ( FFFFH Special function registers (SFR) 256 8 bits FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits Note 1 FB00H FAFFH AFCAN area (256 8 ...
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Processor Registers 78K0/FE2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a ...
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Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) ...
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Figure 3-13. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H (b) CALL, CALLF, CALLT instructions (when SP = FEE0H (c) Interrupt, BRK instructions (when SP = FEE0H ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H SP FEDFH FEDEH SP FEDEH (b) RET instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH FEDEH ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit ...
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Table 3-8. Special Function Register List (1/6) Address Special Function Register (SFR) Name FF00H Port register 0 FF01H Port register 1 FF02H 8-bit timer H compare register 00 FF03H Port register 3 FF04H Port register 4 FF05H Port register 5 ...
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Table 3-8. Special Function Register List (2/6) Address Special Function Register (SFR) Name FF2AH A/D converter mode register FF2BH Analog input channel specification register FF2CH Port mode register 12 FF2DH Port mode register 13 Asynchronous serial interface operation mode FF2EH ...
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Table 3-8. Special Function Register List (3/6) Address Special Function Register (SFR) Name FF51H Prescaler mode register 03 FF52H Capture/compare control register 03 FF53H Asynchronous serial interface reception error status register 60 FF54H 16-bit timer mode control register 02 FF55H ...
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Table 3-8. Special Function Register List (4/6) Address Special Function Register (SFR) Name FF7AH CAN Module Mask 3 Register H FF7BH FF7CH CAN Module Mask 4 Register L FF7DH FF7EH CAN Module Mask 4 Register H FF7FH FF80H Serial operation ...
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Tables 3-8. Special Function Register List (5/6) Address Special Function Register (SFR) Name FFA8H 16-bit timer capture/compare register 003 FFA9H FFAAH 16-bit timer capture/compare register 013 FFABH FFACH Reset control flag register FFADH 16-bit timer mode control register 03 FFAEH ...
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Tables 3-8. Special Function Register List (6/6) Address Special Function Register (SFR) Name FFEAH Priority specification flag register 1L FFEBH Priority specification flag register 1H FFECH 16-bit timer capture/compare register 012 FFEDH FFEEH 8-bit timer H carrier control register 1 ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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... A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn operation code. Register addressing is carried ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] 7 CHAPTER ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved / reset ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION 4.1 Memory Bank μ The PD78F0889, 78F0890 implement a ROM capacity 128 KB by selecting a memory bank from a memory space of 8000H to BFFFH. μ The PD78F0889 has ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.2 Difference in Representation of Memory Space With the 78K0/FE2 products which support the memory bank, addresses can be viewed in the following two different ways. • Memory bank number + CPU address ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( Table 4-1. Memory Bank Address Representation Memory Bank Number CPU Address Memory bank 0 08000H-0BFFFH Memory bank 1 Memory bank 2 Memory bank 3 Memory bank 4 Memory bank 5 Notes 1. SM+ ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( • Software example (to store a value to be referenced in register A) RAMD DSEG SADDR R_BNKA R_BNKN R_BNKRN ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM DATA1 MOVW ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( • Software example 1 (to branch from all areas) RAMD DSEG SADDR R_BNKA R_BNKN RSAVEAX ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM TEST MOVW R_BNKA,#TEST BR !BNKBR : ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( • Software example RAMD DSEG SADDR R_BNKA R_BNKN R_BNKRN RSAVEAX ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM TEST MOVW R_BNKA,#TEST CALL !BNKCAL : : BNKC CSEG ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( Remark Note the following points to use the memory bank select function efficiently. • Allocate a routine that is used often in the common area. • value that is planned to ...
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Port Functions There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. Power Supply AV REF 78K0/FE2 products are provided with the ports shown in Figure 5-1, ...
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Port Configuration Ports include the following hardware. Item Control registers Port mode register (PM0, PM1, PM3 to PM9, PM12, PM13) Port register (P0, P1 P9, P12, P13) Pull-up resistor option register (PU0, PU1, PU3 to PU5, PU7, ...
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Port 0 Port 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00, P01, P05 ...
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Figure 5-3. Block Diagram of P01 and P06 WR PU PU0 PU01, PU06 Alternate function RD WR PORT P0 Output latch (P01, P06 PM0 PM01, PM06 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 ...
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Port 1 Port 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 ...
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Figure 5-5. Block Diagram of P11 and P14 WR PU PU1 PU11, PU14 Alternate function RD WR PORT P1 Output latch (P11, P14 PM1 PM11, PM14 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P12, P13 and P15 WR PU PU1 PU12, PU13, PU15 RD WR PORT P1 Output latch (P12, P13, P15 PM1 PM12, PM13, PM15 Alternate function P1: Port mode register ...
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... Connect P31/TI002/INTP2 as follows when writing the flash memory with a flash programmer. - P31/TI002/INTP2: Connect to EV The above connection is not necessary when writing the flash memory by means of self programming. Remark P31/INTP2/TI002 and P32/INTP3/TI012/TO02 can be used for on-chip debug mode setting when the on-chip debug function is used ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-8. Block Diagram of P32 and P33 WR PU PU3 PU32, PU33 Alternate function RD WR PORT P3 Output latch (P32, P33 PM3 PM32, PM33 Alternate function P3: Port register 3 PU3: Pull-up ...
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Port 4 Port 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up ...
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Port 5 Port 5 is 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor ...
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Port 6 Port 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The P60 to P63 pins ...
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Port 7 Port 7-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P76 ...
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Figure 5-13. Block Diagram of P71 and P75 WR PU PU7 PU71 and PU75 Alternate function RD WR PORT P7 Output latch (P71 and P75 PM7 PM71 and PM75 P7: Port register 7 PU7: Pull-up resistor option register ...
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PORT WR PM P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR××: Write signal CHAPTER 5 PORT FUNCTIONS Figure 5-14. Block Diagram of P72 and ...
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PORT Output latch WR PM Alternate P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR××: Write signal 106 CHAPTER 5 PORT FUNCTIONS Figure 5-15. Block ...
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PORT WR PM P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR××: Write signal CHAPTER 5 PORT FUNCTIONS Figure 5-16. Block Diagram of P76 PU7 ...
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Port 8 Port 8-bit I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (PM8). This port can also be ...
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Port 9 Port 4-bit I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). This port can also be ...
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... Reset signal generation sets port 12 to input mode. Figures 5-19 and 5-20 show block diagrams of port 12. Cautions 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2 input an external clock for the main system clock ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-19. Block Diagram of P120 WR PU PU12 PU120 Alternate function RD WR PORT P12 Output latch (P120 PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode ...
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Figure 5-20. Block Diagram of P121 to P124 RD WR PORT P12 Output latch (P122/P124 PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS RD WR PORT P12 Output latch (P121/P123 PM12 PM121/PM123 OSCCTL OSCSEL/OSCSELS OSCCTL EXCLK/EXCLKS P12: Port register ...
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Port 13 Port 130 is a 1-bit output-only port. Port 131 and 132 are 2-bit I/O port. P131 and P132 can be set to the input mode or output mode in 1-bit units using port mode register 13 (PM13). ...
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WR PU PU13 PU131 Alternate function RD WR PORT P13 Output latch (P131 PM13 PM131 P13: Port register 13 PU13: Pull-up resistor option register 13 PM13: Port mode register 13 RD: Read signal WR××: Write signal 114 CHAPTER ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-23. Block Diagram of P132 WR PU PU13 PU132 Alternate function RD WR PORT P13 Output latch (P132 PM13 PM132 Alternate function P13: Port register 13 PU13: Pull-up resistor option register 13 PM13: ...
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Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3 to PM9, PM12, PM13) • Port registers (P0, P1 P9, P12, P13) • Pull-up resistor ...
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Port mode registers (PM0, PM1, PM3 to PM9, PM12, PM13) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation ...
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Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name TI000 P00 TI010 P01 TO00 SSI11 P05 TI001 TI011 P06 TO01 SCK10 P10 TxD61 SI10 P11 RxD61 SO10 P12 TxD60 P13 RxD60 P14 ...
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Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name SCK11 P76 ANI0-ANI7 P80-P87 ANI8-ANI11 P90-P93 INTP0 P120 EXLVI X1 P121 X2 P122 EXCLK XT1 P123 XT2 P124 EXCLKS TI003 P131 TI013 P132 ...
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Port registers (P0, P1 P9, P12, P13) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level ...
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... PU0, PU1, PU3 to PU5, PU7, PU12, and PU13. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3 to PU5, PU7, PU12, and PU13 ...
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A/D port configuration register (ADPC) This register switches the P80/ANI0 to P87/ANI7 and P90/ANI8 to P93/ANI11 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, ...
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Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject ...
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Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a ...
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Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Control registers Processor clock control register (PCC) Internal oscillator mode register (RCM) Main clock mode register (MCM) Main OSC control register ...
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Clock operation mode Main OSC control register select register (MOC) (OSCCTL) AMPH EXCLK OSCSEL High-speed system clock oscillator f XH X1/P121 Crystal/ceramic f X oscillation X2/EXCLK/ Internal External input P122 f EXCLK high-speed clock oscillator (8 MHz (TYP.)) Subsystem clock ...
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Remarks clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock oscillation frequency Main ...
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Figure 6-2. Format of Processor Clock Control Register (PCC) Address: FFFBH After reset: 01H Symbol 7 6 PCC 0 0 CLS 0 Main system clock 1 Subsystem clock Note 2 CSS PCC2 ...
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Internal oscillator mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H Figure 6-3. Format of Internal ...
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Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ...
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Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU ...
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... External clock input I/O port mode Subsystem clock P123/XT1 pin operation mode I/O port mode I/O port XT1 oscillation mode Crystal resonator connection I/O port mode I/O port External clock input I/O port mode Operating frequency control ≤ 10 MHz XH ≤ 20 MHz XH μ ...
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Cautions 5. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC (the X1 oscillator stops or the external clock from the EXCLK pin is ...
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Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 clock oscillation stabilization time counter. oscillation clock or subsystem clock is used as the CPU clock, the X1 clock oscillation stabilization time can be ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. The wait time set by OSTS is valid only after the STOP mode is ...
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... System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 6-9 shows an example of the external circuit of the X1 oscillator. ...
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... Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 6-11 shows examples of incorrect resonator connection. Figure 6-11. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively ...
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... Figure 6-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning ...
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... When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows. Input (PM123/PM124 = 1): Independently connect to V Output (PM123/PM124 = 0): Leave open ...
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... When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the on-chip internal high-speed oscillation clock, so the device can be started by the internal high- speed oscillation clock after a reset release ...
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Figure 6-12 Operation of the clock generating circuit when power supply voltage injection (When 1.59 V POC mode setup (option byte: LVISTART = 0)) Power supply 1.8 V voltage ( 1.59 V (TYP.) 0.5 V/ms (MIN ...
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... Figure 6-12 or subsequent ones. 2. When using the external clock input from EXCLK pin and EXCLKS pin, oscillation stable waiting time is unnecessary. remark The clock which is not used as a CPU clock can be suspended by setup of software during microcomputer operation. Moreover, high-speed oscillation clock and a high-speed system clock can suspend a clock by execution of a STOP command (see ( ...
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... V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time 5. automatically generated before reset processing not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. 144 CHAPTER 6 CLOCK GENERATOR 2 ...
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... The following two types of high-speed system clocks are available. • X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins. • External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port pins ...
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... Setting high-speed system clock oscillation (See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when high-speed system clock is already operating. 146 CHAPTER 6 CLOCK GENERATOR Operating Frequency Control ≤ ...
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Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of ...
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... Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the CPU clock. 2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral hardware clock. (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock < ...
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... Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0. ...
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... The following two types of subsystem clocks are available. • XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. • External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins. ...
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... Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using the external subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2> Switching the CPU clock (PCC register) When CSS is set to 1, the subsystem clock is supplied to the CPU. ...
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Controlling internal low-speed oscillation clock The internal low-speed oscillation clock is a clock for the watchdog timer. It cannot be used as the CPU clock. With this clock, only the following peripheral hardware can operate. • Watchdog timer • ...
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CPU clock status transition diagram Figure 6-14 shows the CPU clock status transition diagram of this product. Figure 6-14. CPU Clock Status Transition Diagram Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Internal low-speed oscillation: Operable ...
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... SFR Register Setting SFR registers do not have to be set (default status after reset release). EXCLKS OSCSELS User’s Manual U17554EJ4V0UD MSTOP OSTC XSEL MCM0 Register 0 Must checked Must not be checked 0 Must checked Must not be checked Waiting for CSS Oscillation Stabilization Necessary 1 Unnecessary 1 ...
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... Bit 4 of the processor clock control register (PCC) CHAPTER 6 CLOCK GENERATOR AMPH EXCLK OSCSEL Unnecessary if these registers are already set EXCLKS OSCSELS Unnecessary if the CPU is operating with the subsystem clock User’s Manual U17554EJ4V0UD MSTOP OSTC XSEL MCM0 Register 0 Must checked Must not be checked 0 Must checked 0 1 ...
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... CSS: Bit 4 of the processor clock control register (PCC) RSTS, RSTOP: Bits 7 and 0 of the internal oscillator mode register (RCM) 156 CHAPTER 6 CLOCK GENERATOR RSTOP 0 Confirm this flag is 1. Unnecessary if the CPU is operating with the internal high-speed oscillation clock EXCLKS OSCSELS ...
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... RSTS, RSTOP: Bits 7 and 0 of the internal oscillator mode register (RCM) CHAPTER 6 CLOCK GENERATOR RSTOP RSTS 0 Confirm this flag is 1. Unnecessary if the CPU is operating with the internal high-speed oscillation clock Executing HALT instruction Stopping peripheral functions that cannot operate in STOP mode User’s Manual U17554EJ4V0UD MCM0 ...
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Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. CPU Clock Before Change After Change Internal high- X1 clock Stabilization of ...
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Time required for switchover of CPU clock and main system clock By setting bits (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the ...
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Table 6-7. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover MCM0 0 1 Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS The 78K0/FE2 incorporates 16-bit timer/event counters 00 to 03. 7.1 Functions of 16-Bit Timer/Event Counters 16-bit timer/event counters have the following functions. • Interval timer • ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 7.2 Configuration of 16-Bit Timer/Event Counters 16-bit timer/event counters include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters Item Timer counter ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 Noise TI011/TO01/P06 elimi- nator f PRS PRS PRS ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-4. Block Diagram of 16-Bit Timer/Event Counter 03 Internal bus Capture/compare control register 03 (CRC03) CRC032CRC031 CRC030 Noise elimi- TI013/TO03/P132 nator f PRS PRS PRS ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (2) 16-bit timer capture/compare register 00n (CR00n) CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger Falling ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (4) Setting range when CR00n or CR01n is used as a compare register When CR00n or CR01n is used as a compare register, set it as shown below. Operation Operation as interval ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Table 7-4. Capture Operation of CR00n and CR01n External Input Signal TI00n Pin Input Capture Operation Capture operation of CRC0n1 = 1 CR00n TI00n pin input (reverse phase) Interrupt signal Note Capture ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 7.3 Registers Controlling 16-Bit Timer/Event Counters The following six registers are used to control 16-bit timer/event counters 00 to 03. • 16-bit timer mode control register 0n (TMC0n) • ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-8. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol 7 6 TMC00 0 0 TMC003 TMC002 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-9. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H Symbol 7 6 TMC01 0 0 TMC013 TMC012 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-10. Format of 16-Bit Timer Mode Control Register 02 (TMC02) Address: FF54H After reset: 00H Symbol 7 6 TMC02 0 0 TMC023 TMC022 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-11. Format of 16-Bit Timer Mode Control Register 03 (TMC03) Address: FFADH After reset: 00H Symbol 7 6 TMC03 0 0 TMC033 TMC032 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-13. Example of CR01n Capture Operation (When Rising Edge Is Specified) Count clock TM0n TI00n Rising edge detection CR01n INTTM01n Remark Figure 7-14. Format of Capture/Compare ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-15. Format of Capture/Compare Control Register 02 (CRC02) Address: FF5CH After reset: 00H Symbol 7 6 CRC02 0 0 CRC022 0 Operates as compare register 1 Operates as capture register CRC021 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-16. Format of Capture/Compare Control Register 03 (CRC03) Address: FF52H After reset: 00H Symbol 7 6 CRC03 0 0 CRC032 0 Operates as compare register 1 Operates as capture register CRC031 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (3) 16-bit timer output control register 0n (TOC0n) TOC0n is an 8-bit register that controls the TO0n pin output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-17. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> TOC00 0 OSPT00 OSPT00 0 1 One-shot pulse output The value of ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-18. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol 7 <6> TOC01 0 OSPT01 OSPT01 0 1 One-shot pulse output The value of this ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-19. Format of 16-Bit Timer Output Control Register 02 (TOC02) Address: FFA5H After reset: 00H R/W Symbol 7 <6> TOC02 0 OSPT02 OSPT02 0 1 One-shot pulse output The value of ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-20. Format of 16-Bit Timer Output Control Register 03 (TOC03) Address: FFF9H After reset: 00H Symbol 7 <6> TOC03 0 OSPT03 OSPT03 0 1 One-shot pulse output The value of this ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-21. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H Symbol 7 6 PRM00 ES101 ES100 ES101 ES100 ES001 ES000 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-22. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol 7 6 PRM01 ES111 ES110 ES111 ES110 ES011 ES010 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-23. Format of Prescaler Mode Register 02 (PRM02) Address: FF59H After reset: 00H Symbol 7 6 PRM02 ES121 ES120 ES121 ES120 ES021 ES020 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-24. Format of Prescaler Mode Register 03 (PRM03) Address: FF51H After reset: 00H Symbol 7 6 PRM03 ES131 ES130 ES131 ES130 ES031 ES030 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (7) Port mode register 13 (PM13) This register sets port 13 input/output in 1-bit units. When using the P132/TO03/TI013 pin for timer output, set PM132 and the output latch of P132 to ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 7.4 Operation of 16-Bit Timer/Event Counters 7.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-28 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-28. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n TMC0n3 TMC0n (b) Capture/compare control register 0n ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-29. Interval Timer Configuration Diagram Note PRS PRS Note PRS PRS 8 6 Note ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 7.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-31 allows operation as PPG (Programmable Pulse Generator) output. Setting ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-31. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n TMC0n (b) Capture/compare control register 0n (CRC0n) ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-32. Configuration Diagram of PPG Output Note PRS PRS Note PRS PRS 8 6 Note PRS ...
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... When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 0n (PRM0n) and the valid level of the TI00n or TI01n pin is detected twice, thus eliminating noise with a short pulse width ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS Figure 7-36. Configuration Diagram for Pulse Width Measurement with Free-Running Counter Note PRS PRS 2 4 Note PRS PRS 8 6 Note f /2 ...