UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 459

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

16.9.2 Receive Data Read
to 16-53.
storage process of data to the message buffer, and again at the end of this storage process. During this storage
process, the MUC bit of the C0MCTRLm register of the message buffer is set. (Refer to Figure 16-29.)
1), the RDY bit of the C0MCTRL register of the message buffer is locked to avoid the coincidental data WR by CPU.
Note the storage process may be disturbed (delayed) when the CPU accesses the message buffer.
CAN std ID format
Remark m = 0 to 15
To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 16-51
During message reception, the CAN module sets DN of the C0MCTRLm register two times: at the beginning of the
The receive history list is also updated just before the storage process. In addition, during storage process (MUC =
INTREC1
Operation of the CAN contoroller
CINTS1
MUC
DN
(1)
Figure 16-29. DN and MUC Bit Setting Period (for Standard ID Format)
(11)
ID
(1)
(1)
(1)
DLC
(4)
CHAPTER 16 CAN CONTROLLER
DATA0-DATA7
User’s Manual U17554EJ4V0UD
(0-64)
CRC
(16)
ACK EOF
(2)
(7)
MDATA,MDLC.MIDx- > MBUF
Set DN & MUC
at the same time
Message Store
IFS
Set DN & clear MUC
at the same timing
Recessive
Dominant
459