UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 150

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

6.6.3 Example of controlling subsystem clock
150
(1) Example of setting procedure when oscillating the XT1 clock
The following two types of subsystem clocks are available.
• XT1 clock:
• External subsystem clock: External clock is input to the EXCLKS pin.
When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins.
The following describes examples of setting procedures for the following cases.
(1) When oscillating XT1 clock
(2) When using external subsystem clock
(3) When using subsystem clock as CPU clock
(4) When stopping subsystem clock
Caution The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release.
(b) To stop internal high-speed oscillation clock by setting RSTOP to 1
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop
<1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
<2> Waiting for the stabilization of the subsystem clock oscillation
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
<1> Confirming the CPU clock status (PCC and MCM registers)
<2> Stopping the internal high-speed oscillation clock (RCM register)
When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from
port mode to XT1 oscillation mode.
Remark
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
XTSTART
CLS
0
0
1
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to the high-speed system clock or subsystem clock.
When RSTOP is set to 1, internal high-speed oscillation clock is stopped.
peripheral hardware that is operating on the internal high-speed oscillation clock.
operating.
0
1
×: don’t care
EXCLKS
MCS
×
0
1
0
×
Crystal/ceramic resonator is connected across the XT1 and XT2 pins.
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
OSCSELS
1
CHAPTER 6 CLOCK GENERATOR
×
User’s Manual U17554EJ4V0UD
XT1 oscillation mode
Subsystem Clock Pin
Operation Mode of
CPU Clock Status
Crystal/ceramic resonator connection
P123/XT1 Pin
EXCLKS Pin
P124/XT2/