UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 416

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
Caution The actual register address is calculated as follows:
Remark (R) When read
416
FF90H
FF91H
FF90H
FF91H
FF92H
FF92H
FF93H
FF94H
FF95H
FF96H
FF97H
FF96H
FF97H
FF98H
FF99H
FF98H
FF99H
FF9CH
FF9DH
FF9EH
FF9FH
Address
(W) When write
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
C0CTRL(W)
C0CTRL(R)
C0LEC(W)
C0LEC(R)
C0INFO
C0ERC
C0IE(W)
C0IE(R)
C0INTS(W)
C0INTS(R)
C0BTR
C0BRP
C0LIPT
Symbol
Table 16-18. Bit Configuration of CAN Module Registers (2/2)
CCERC
CCERC
CCERC
Bit 7/15
Clear
Set
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAPTER 16 CAN CONTROLLER
Bit 6/14
Clear
Set
AL
AL
AL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
User’s Manual U17554EJ4V0UD
Clear CIE5 Clear CIE4 Clear CIE3 Clear CIE2 Clear CIE1 Clear CIE0
Set CIE5
CINTS5
Bit 5/13
CINTS5
VALID
VALID
Clear
Clear
CIE5
0
0
0
0
0
0
0
0
0
SJW[1:0]
PSMODE
PSMODE
Set CIE4
CINTS4
Bit 4/12
MODE1
CINTS4
BOFF
Clear
Clear
CIE4
Set
PS
0
0
0
0
0
0
0
1
1
TQPRS[7:0]
REC[7:0]
LIPT[7:0]
TEC[7:0]
PSMODE
PSMODE
Set CIE3
MODE0
CINTS3
CINTS3
Bit 3/11
TECS1
Clear
Clear
CIE3
Set
PS
0
0
0
0
0
0
0
0
0
OPMODE
OPMODE
Set CIE2
CINTS2
Bit 2/10
MODE2
CINTS2
TECS0
Clear
LEC2
Clear
CIE2
Set
OP
2
2
0
0
0
0
0
TSEG1[3:0]
TSEG2[2:0]
OPMODE
OPMODE
Set CIE1
CINTS1
MODE1
CINTS1
RSTAT
RECS1
Bit 1/9
LEC1
Clear
Clear
CIE1
Set
OP
0
0
0
0
1
1
OPMODE
OPMODE
Set CIE0
CINTS0
MODE0
RECS0
CINTS0
TSTAT
Bit 0/8
LEC0
Clear
Clear
CIE0
Set
OP
0
0
0
0
0
0

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