UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 396

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

396
Receiving node detects an error (except bit error in the active error flag
or overload flag).
Receiving node detects dominant level following error flag of error
frame.
Transmitting node transmits an error flag.
[As exceptions, the error counter does not change in the following
cases.]
<1> ACK error is detected in error passive state and dominant level is
<2> A stuff error is detected in an arbitration field that transmitted a
Bit error detection while active error flag or overload flag is being output
(error-active transmitting node)
Bit error detection while active error flag or overload flag is being output
(error-active receiving node)
When the node detects 14 consecutive dominant-level bits from the
beginning of the active error flag or overload flag, and then subsequently
detects 8 consecutive dominant-level bits. When the node detects 8
consecutive dominant levels after a passive error flag
When the transmitting node has completed transmission without error
(±0 if error counter = 0)
When the receiving node has completed reception without error
recessive level as a stuff bit, but a dominant level is detected.
not detected while the passive error flag is being output.
(b) Error counter
(c) Occurrence of bit error in intermission
The error counter counts up when an error has occurred, and counts down upon successful transmission
and reception. The error counter is updated immediately after error detection.
An overload frame is generated.
Caution If an error occurs, the error flag output (active or passive) is controlled according to the
contents of the transmission error counter and reception error counter before the error
occurred. The value of the error counter is incremented after the error flag has been
output.
State
CHAPTER 16 CAN CONTROLLER
Table 16-14. Error Counter
User’s Manual U17554EJ4V0UD
Transmission Error Counter
No change
No change
No change
+8
+8
No change
+8 (during transmission)
–1
(TEC7 to TEC0)
+1 (when REPS bit = 0)
+8 (when REPS bit = 0)
No change
No change
+8 (when REPS bit = 0)
+8 (during reception,
when REPS bit = 0)
No change
- –1 (1 ≤ REC6 to REC0
- ±0 (REC6 to REC0 = 0,
- Value of 119 to 255 is
Reception Error Counter
≤ 127, when REPS bit =
0)
when REPS bit = 0)
set (when REPS bit = 1)
(REC6 to REC0)