UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 168

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(3) 16-bit timer capture/compare register 01n (CR01n)
Cautions 1. If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated when the
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 is prohibited.
168
Falling edge
Rising edge
Both rising and falling edges
CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n
(CRC0n).
CR01n can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
• When CR01n is used as a compare register
• When CR01n is used as a capture register
The value set in the CR01n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an
interrupt request (INTTM01n) is generated if they match. The set value is held until CR01n is rewritten.
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set by
prescaler mode register 0n (PRM0n) (see Table 7-3).
3. n = 0 to 3
CR01n Capture Trigger
2. When CR01n is used as a capture register, read data is undefined if the register read time and
3. CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 7-33 PPG
2. ES0n1, ES0n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n)
(n = 0 to 3)
Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011)
Symbol
CR01n
value of CR01n changes from 0000H to 0001H following TM0n overflow (FFFFH). In addition,
INTTM01n is generated after a match between TM0n and CR01n, after detecting the valid edge of
the TI00n pin, and the timer is cleared by a one-shot trigger.
capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
Output Operation Timing.
CRC0n2:
Table 7-3. CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1)
Figure 7-7. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
FFECH, FFEDH (CR012), FFAAH, FFABH (CR013)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
Bit 2 of capture/compare control register 0n (CRC0n)
FFEDH (CR012)
FFABH (CR013)
FFB5H (CR011)
FF15H (CR010)
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U17554EJ4V0UD
TI00n Pin Valid Edge
After reset: 0000H
FFECH (CR012)
FFB4H (CR011)
FFAAH (CR013)
FF14H (CR010)
ES0n1
0
0
1
R/W
ES0n0
0
1
1