UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 294

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(5) A/D port configuration register (ADPC)
294
This register switches the P80/ANI0 to P87/ANI7, P90/ANI8 to P93/ANI11 pins to analog input of A/D converter or
digital I/O of port.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. Set the channel to be used for A/D conversion in the input mode by using port mode
ADPC3 ADPC2 ADPC1 ADPC0
Address: FF22H
Symbol
ADPC
0
0
0
0
0
0
0
0
1
1
1
1
1
Other than above
2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the
0
0
0
0
1
1
1
1
0
0
0
0
1
register 8, 9 (PM8, PM9).
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
7
0
0
0
1
1
0
0
1
1
0
0
1
1
0
After reset: 00H
Figure 13-9. Format of A/D Port Configuration Register (ADPC)
0
1
0
1
0
1
0
1
0
1
0
1
0
6
0
Setting prohibited
ANI11
P93/
A
A
A
A
A
A
A
A
A
A
A
A
D
R/W
ANI10
P92/
CHAPTER 13 A/D CONVERTER
A
A
A
A
A
A
A
A
A
A
A
D
D
User’s Manual U17554EJ4V0UD
5
0
ANI9
P91/
A
A
A
A
A
A
A
A
A
A
D
D
D
ANI8
Analog input (A)/ digital I/O (D) switching
P90/
A
A
A
A
A
A
A
A
A
D
D
D
D
4
0
ANI7
P87/
D
D
D
D
D
A
A
A
A
A
A
A
A
ADPC3
ANI6
P86/
D
D
D
D
D
D
A
A
A
A
A
A
A
3
ANI5
P85/
D
D
D
D
D
D
D
A
A
A
A
A
A
ADPC2
ANI4
P84/
2
A
A
A
A
A
D
D
D
D
D
D
D
D
ANI3
P83/
A
A
A
A
D
D
D
D
D
D
D
D
D
ADPC1
1
ANI2
P82/
A
A
A
D
D
D
D
D
D
D
D
D
D
ANI1
P81/
A
A
D
D
D
D
D
D
D
D
D
D
D
ADPC0
0
ANI0
P80/
D
D
D
D
D
D
D
D
D
D
D
D
A

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