UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 309
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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Reception interrupt
Reception processing is as follows.
Remark n = 0, 1
Edge detection
<1> The wakeup signal is detected at the edge of the pin, and enables UART6n and sets the SBF reception
<2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has
<3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter
<4> Calculate the baud rate error from the bit length of the sync field, disable UART6n after SF reception, and
<5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6n after
Capture timer
(INTSR6n)
mode.
been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is
output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF
reception of the checksum field and to set the SBF reception mode again.
reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored.
00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field
(see 7.4.3
suppressed, and error detection processing of UART communication and data transfer of the shift register
and RXB6n is not performed. The shift register holds the reset value FFH.
then re-set baud rate generator control register 6n (BRGC6n).
(INTPn)
LIN bus
RXD6n
Disable
Pulse width measurement operation).
signal frame
<1>
Wakeup
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
Enable
Figure 14-2. LIN Reception Operation
Disable
SBF reception
break field
User’s Manual U17554EJ4V0UD
Sync
13-bit
<2>
<3>
reception
Sync
field
SF
Enable
Detection of errors OVE6n, PE6n, and FE6n is
<4>
reception
Identifer
field
ID
Data field
reception
Data
Data field Checksum
reception
Data
reception
Data
field
<5>
309
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