UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 519

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Maskable
Notes 1. The default priority is the priority applicable when two or more maskable interrupt are generated
Interrupt
Type
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 17-1.
3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 0.
simultaneously. 0 is the highest priority, and 28 is the lowest.
Priority
Default
10
11
12
13
14
15
16
0
1
2
3
4
5
6
7
8
9
Note 1
INTLVI
INTP0
INTP1
INTP2
INTTM002
INTP3
INTTM012
INTP4
INTTM003
INTP5
INTTM013
INTC0ERR
INTC0WUP
INTC0REC
INTC0TRX
INTSRE60
INTSR60
INTST60
INTCSI10
INTSRE61
INTP6
INTSR61
INTP7
INTST61
Name
Table 17-1. Interrupt Source List (1/2)
CHAPTER 17 INTERRUPT FUNCTIONS
Low-voltage detection
Pin input edge detection
Pin input edge detection
Match between TM02 and CR002
(when compare register is specified),
TI012 pin valid edge detection
(when capture register is specified)
Pin input edge detection
Match between TM02 and CR012
(when compare register is specified),
TI002 pin valid edge detection
(when capture register is specified)
Pin input edge detection
Match between TM03 and CR003
(when compare register is specified),
TI013 pin valid edge detection
(when capture register is specified)
Pin input edge detection
Match between TM03 and CR013
(when compare register is specified),
TI003 pin valid edge detection
(when capture register is specified)
AFCAN0 error occurrence
AFCAN0 wakeup
AFCAN0 reception completion
AFCAN0 transmission completion
UART60 reception error generation
End of UART60 reception
End of UART60 transmission
End of CSI10 transmission
UART61 reception error generation
Pin input edge detection
End of UART61 reception
Pin input edge detection
End of UART61 transmission
Interrupt Source
User’s Manual U17554EJ4V0UD
Trigger
Note 3
Internal
External
Internal
External
Internal
External
Internal
External
Internal/
Address
000AH
000CH
000EH
001AH
001CH
001EH
0004H
0006H
0008H
0010H
0012H
0014H
0016H
0018H
0020H
0022H
0024H
Vector
Table
Configuration
Type
Basic
(A)
(B)
(A)
(B)
(A)
(B)
(A)
Note 2
519