UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 348

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
348
R
RxD61/P11SI10
X
D60/P14
(g) Noise filter of receive data
The RXD6n signal’s is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 14-29, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Base clock
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
In
Figure 14-29. Noise Filter Circuit
Q
User’s Manual U17554EJ4V0UD
Internal signal A
Match detector
In
LD_EN
Q
Internal signal B

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