ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 421

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

KNOWN LIMITATIONS (Cont’d)
Impact On Apllication
1. The MFT1 wins the next DMA Arbitration, the
2. The MFT1 does not win the next DMA Arbitra-
pare value is used twice.
3. The MFT1 wins the next DMA Arbitration, the
DMA request is serviced.
The MFT0 interrupt routine is executed before
the next Input Capture or Output Compare
event. It detects that a wrong Mask Bit Reset
has occurred on the MFT1 and re-enables the
DMA Mask.
tion, the DMA request is not serviced. The
MFT1 will not request the DMA again as its
DMA Mask bit is reset.
DMA request is serviced.
The MFT0 interrupt routine is not executed
before the next MFT1 Input Capture or Output
Compare event. This new event generates an
Interrupt. The interrupt routine must check
that the DMA counter is equal to 0. If it is not
equal to 0, the DMA counter and address
must not be changed, but the DMA Mask
must be set.
If this failure recovery management can be
executed fast enough within the interrupt rou-
tine, there is no impact on the application.
Otherwise the counter will reach the new
compare value before it has been loaded in
the Compare Register or a new input capture
event will occur before the previous value has
been saved.
=> An Input Capture value or a Comparison
value must be handled by the interrupt rou-
tine.
=> There is no application impact.
=> A DMA transfer is lost.
The MFT0 interrupt routine is executed be-
=> An Input Capture value is lost or a Com-
fore the next Input Capture or Output Com-
pare event. It detects that a wrong Mask Bit
Reset has occurred on the MFT1 and re-ena-
bles the DMA Mask.
ST92F124/F150/F250 - KNOWN LIMITATIONS
4.
Workaround
If it is not possible to limit the DMA to one MFT
only (no DMA with another MFT, SCI-M or I2C),
the following failure recovery management must
be included in the MFT, SCI-M, I2C Interrupt rou-
tines (if the DMA is used).
1. Following an End-of-Block event (DMA coun-
2. Following an Input Capture or an Output
The MFT0 interrupt routine is not executed
before the next MFT1 Input Capture or Output
Compare event. This new event generates an
Interrupt. The interrupt routine must check
that the DMA counter is equal to 0. If it is not
equal to 0, the DMA counter and address
must not be changed, but the DMA Mask
must be set.
executed fast enough within the interrupt rou-
tine, only one transfer is lost. Otherwise the
counter will reach the new compare value
before it has been loaded in the Compare
Register or a new input capture event will
occur before the previous value has been
saved.
ter equal to 0):
Check the other MFT DMA counter (both
MFTs if this is the SCI-M or the I2C interrupt
routine). If the counter does not equal 0 and
the DMA mask is reset, reset the interrupt flag
bit, set the DMA Mask bit.
Compare event (DMA counter does not equal
0):
Execute the transfer by software, modify the
DMA counter and address, reset the interrupt
flag bit, set the DMA Mask bit.
If this failure recovery management can be
=> A DMA transfer is lost.
=> An Input Capture value or a Comparison
value must be handled by the interrupt rou-
tine.
tration, the DMA request is not serviced. The
MFT1 will not request the DMA again as its
DMA Mask bit is reset.
The MFT1 does not win the next DMA Arbi-
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