ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 267

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

I
Then the slave address is sent to the SDA line.
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the
I2CSR1.EVF and I2CSR1.ADD10 bits to be set by
hardware
I2CCR.ITE bit is set.
Then the master waits for a read of the I2CSR1
register followed by a write in the I2CDR register,
holding the SCL line low (see
fer sequencing EV9). Then the second address
byte is sent by the interface.
After each address byte, an acknowledge clock
pulse is sent to the SCL line if the I2CSR1.EVF
and
– I2CSR1.ADD10 bit (if first header)
– I2CSR2.ADDTX bit (if address or second head-
are set, and an interrupt is generated if the
I2CCR.ITE bit is set.
The peripheral waits for a read of the I2CSR1 reg-
ister followed by a write into the Control Register
(I2CCR) by holding the SCL line low (see
128
If there was no acknowledge (I2CSR2.AF=1), the
master must stop or restart the communication
(set the I2CCR.START or I2CCR.STOP bits).
If there was an acknowledge, the state machine
enters a sending or receiving process according to
the data direction bit (least significant bit of the ad-
dress), the I2CSR1.BTF flag is set and an interrupt
is generated if I2CCR.ITE bit is set (see Transfer
sequencing EV7, EV8 events).
If the master loses the arbitration of the bus there
is no acknowledge, the I2CSR2.AF flag is set and
the master must set the START or STOP bit in the
control register (I2CCR).The I2CSR2.ARLO flag is
set, the I2CSR1.M/SL flag is cleared and the proc-
ess is reset. An interrupt is generated if I2CCR.ITE
is set.
Master Transmitter:
The master waits for the microcontroller to write in
the Data Register (I2CDR) or it waits for the DMA
to complete both holding the SCL line low (see
Transfer sequencing EV8).
Then the byte is received into the shift register and
sent to the SDA line. When the acknowledge bit is
received, the I2CSR1.BTF flag is set and an
interrupt is generated if the I2CCR.ITE bit is set or
the DMA is requested.
2
C BUS INTERFACE (Cont’d)
er)
Transfer sequencing EV6 event).
with
interrupt
generation
Figure 128
if
Trans-
Figure
the
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Master Receiver:
The master receives a byte from the SDA line into
the shift register and sends it to the I2CDR regis-
ter. It generates an acknowledge bit if the
I2CCR.ACK bit is set and an interrupt if the
I2CCR.ITE bit is set or a DMA is requested (see
Transfer sequencing EV7 event).
Then it waits for the microcontroller to read the
Data Register (I2CDR) or waits for the DMA to
complete both holding SCL line low.
Error Cases
■
■
■
Note: In all cases, to resume communications, set
the I2CCR.START or I2CCR.STOP bits.
Events generated by the I
■
■
BERR: Detection of a Stop or a Start condition
during a byte transfer.
The I2CSR2.BERR flag is set and an interrupt is
generated if I2CCR.ITE is set.
AF: Detection of a no acknowledge bit
The I2CSR2.AF flag is set and an interrupt is
generated if I2CCR.ITE is set.
ARLO: Arbitration Lost
The I2CSR2.ARLO flag is set, the I2CSR1.M/SL
flag is cleared and the process is reset. An
interrupt is generated if the I2CCR.ITE bit is set.
STOP condition
When the I2CCR.STOP bit is set, a Stop
condition is generated after the transfer of the
current byte, the I2CSR1.M/SL flag is cleared
and the state machine is reset. No interrupt is
generated in master mode at the detection of
the stop condition.
START condition
When the I2CCR.START bit is set, a start
condition is generated as soon as the I
free. The I2CSR1.SB flag is set and an interrupt
is generated if the I2CCR.ITE bit is set.
I2C BUS INTERFACE
2
C interface
2
C bus is
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