ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 236

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
SYNCHRONOUS OUTPUT CONTROL (SOCR)
R255 - Read/Write
Reset value: 0000 0001 (01h)
Bit 7 = OUTPL: SOUT Output Polarity.
0: Polarity not inverted.
1: Polarity inverted.
Note: OUTPL only affects the data sent by the
transmitter section. In Auto-Echo mode SOUT =
SIN even if OUTPL=1. In Loop-Back mode, the
state of OUTPL is irrelevant.
Bit 6 = OUTSB: SOUT Output Stand-By Level.
0: SOUT stand-by level is HIGH.
1: SOUT stand-by level is LOW.
Bit 5 = OCKPL: Transmitter Clock Polarity.
0: CLKOUT is active on the rising edge.
1: CLKOUT is active on the falling edge.
Note: OCKPL only affects the transmitter clock. In
Auto-Echo mode CLKOUT = RXCLK independ-
ently of the state of OCKPL. In Loop-Back mode
the state of OCKPL is irrelevant.
Bit 4 = OCKSB: Transmitter Clock Stand-By Lev-
el.
0: The CLKOUT stand-by level is HIGH.
1: The CLKOUT stand-by level is LOW.
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9
OUTP
7
L
OUTS
B
OCKP
L
OCKS
B
RTSE
N
RTS
PL
OUT
DIS
X
0
Bit 3 = RTSEN: RTS and SDS Output Enable.
0: Disable the RTS and SDS hardware synchroni-
1: Enable the RTS and SDS hardware synchroni-
Notes:
– When RTSEN is set, the RTS output becomes
– When RTSEN is set, the SDS output becomes
Bit 2 = RTSPL: RTS Output Polarity.
0: The RTS output is active when LOW.
1: The RTS output is active when HIGH.
Note: RTSPL only affects the RTS activity on the
output pin. In Auto-Echo mode RTS = DCD inde-
pendently from the RTSPL value. In Loop-Back
mode RTSPL value is 'Don't Care'.
Bit 1 = OUTDIS: Disable all outputs.
This feature is available on specific devices only
(see device pin-out description).
When OUTDIS=1, all output pins (if configured in
Alternate Function mode) will be put in High Im-
pedance for networking.
0: SOUT/CLKOUT/enabled
1: SOUT/CLKOUT/RTS put in high impedance
Bit 0 = “Don't Care”
active just before the first active edge of CLK-
OUT and indicates to target device that the MCU
is about to send a synchronous frame; it returns
to its stand-by value just after the last active edge
of CLKOUT (MSB transmitted).
active high and indicates to the target device that
the MCU is about to send the first bit of a syn-
chronous frame on the Serial Output Pin
(SOUT); it returns to low level as soon as the
second bit is sent on the Serial Output Pin
(SOUT). In this way a positive pulse is generated
each time that the first bit of a synchronous frame
is present on the Serial Output Pin (SOUT).
sation.
sation.