ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 277

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

I
I
(I2CCCR)
R243 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM Fast/Standard I
This bit is used to select between fast and stand-
ard mode. See the description of the following bits.
It is set and cleared by software. It is not cleared
when the peripheral is disabled (I2CCR.PE=0)
Bits 6:0 = CC[6:0] 9-bit divider programming
Implementation of a programmable clock divider.
These bits and the CC[8:7] bits of the I2CECCR
register select the speed of the bus (F
pending on the I
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Refer to the Electrical Characteristics section for
the table of values
Note: The programmed frequency is available
with no load on SCL and SDA pins.
2
2
FM/SM
C BUS INTERFACE (Cont’d)
C CLOCK CONTROL REGISTER
7
CC6
2
CC5
C mode.
(Table 70 on page
CC4 CC3 CC2 CC1 CC0
2
C mode.
399).
SCL
) de-
0
I
(I2COAR1)
R244 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
7-bit Addressing Mode
Bits 7:1 = ADD[7:1] Interface address.
These bits define the I
face.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care; the interface acknowledges
either 0 or 1.
It is not cleared when the interface is disabled
(I2CCR.PE=0).
Note: Address 01h is always ignored.
10-bit Addressing Mode
Bits 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I
address of the interface.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
2
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
C OWN ADDRESS REGISTER 1
7
2
C bus address of the inter-
I2C BUS INTERFACE
277/429
2
Cbus
0
9