ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 110

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
INTERRUPT
(SIPRL)
R250 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:0 = IPxx Channel E-H Pending bits
The IPxx bits are set by hardware on occurrence
of the trigger event. (as specified in the ITR regis-
ter) and are cleared by hardware on interrupt ac-
knowledge.
0 : No interrupt pending
1 : Interrupt pending
Note: IPR bits may be set by the user to imple-
ment a software interrupt.
STANDARD INTERRUPT VECTOR REGISTER
(SIVR)
R251 - Read/Write
Register Page: 60
Reset value: xxx1 1110 (xE)
Bits 7:5 = V[7:5] MSBs of Channnel E to L inter-
rupt vector address
These bits are not initialized by reset. For a repre-
sentation of how the full vector is generated from
V[7:5], refer to
110/429
9
IPH1
V7
7
7
IPH0
V6
IPG1
V5
Figure
PENDING
IPG0
W3
53.
IPF1
W2
REGISTER
IPF0
W1
IPE1
W0
IPE0
LOW
0
0
0
Bits 4:1 = W[3:0] Arbitration Winner Bits
These bits are set and cleared by hardware de-
pending upon the channel which emerges as a
winner as shown in the following table.
At the start of interrupt/DMA arbitration (IC0 = 0)
the W[3:0] bits are latched. They remain stable
through the entire arbitration cycle. Even if a inter-
rupt of higher priority comes after the start of int/
DMA arbitration, the SIVR register is not updated.
This new request will be taken into account in the
next arbitration cycle.
Bit 0 = Reserved, fixed by hardware to 0.
INTERRUPT
HIGH (SIPLRH)
R252 - Read/Write
Register Page: Page 60
Reset Value : 1111 1111
Bits 1:0 = PL2I, PL1I: INTI0, I1 Priority Level.
These bits are set and cleared by software.
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for even channels and at 1 for odd
channels
7
Interrupt Channel pair
-
-
INTG0
INTG1
INTE0
INTE1
INTH0
INTH1
INTF0
INTF1
INTI0
PRIORITY
-
-
-
LEVEL
-
W[3:0]
1000
REGISTER
0000
0001
0010
0011
0100
0101
0110
0111
PL2I
PL1I
0