ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 414

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.6 CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING
Description
Under certain conditions, FIFO corruption can
occur in the following cases:
WHEN a bxCAN RX FIFO already holds 2 mes-
sages (i.e. FMP==2)
Figure 2. FIFO Corruption
414/429
1
and Receive Message D
AND the application releases the same FIFO
Receive Message C
Release Message A
Release Message B
Release Message C
Release Message E
Release Message B
Receive Message A
Receive Message B
Receive Message E
(with the instruction CANx_CTRL_CRFRy |=
CRF_rfom;
x=0 for the CAN_0 cell
x=1 for the CAN_1 cell
y=0 for the Receive FIFO 0
y=1 for the Receive FIFO 1 )
* pointer to next receive location
v pointer to next message to be released
Initial State
FMP
0
1
2
3
2
2
3
2
1
0
v
E B C
v
v
v
A B C
E B C
E B C
* v
- - -
A - -
A B -
A B C
D B C
D B C
E B C
*
FIFO
*
*
v
* v
*
*
* v
v
*
*
*
v
v
When the FIFO is empty, v and * point to the same location
E released instead of B
* does not move because FIFO is full (normal operation)
D is overwritten by E
C released
* and v are not pointing to the same message
the FIFO is empty
* Does not move, pointer curruption
Normal operation
WHILE the bxCAN requests the transfer of a new
receive message into the FIFO (this lasts one CPU
cycle)
Impact on Application:
As the FIFO pointer is not updated correctly, this
causes the last message received to be over-
written by any incoming message. This means one
message is lost as shown in the example in
2
until a device reset occurs.
The bxCAN will not recover normal operation
THEN the internal FIFO pointer is not updated
BUT the FMP bits are updated correctly
Figure