ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 294

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Received Message Filtering
The FREG[0:31] registers can be considered an
array of 256 bits (the FREG[0].0 bit is bit 0 of the
array and the FREG[31].7 bit is bit 255). The I.D.
byte of a message frame is used as a pointer to
the array (See
Upon the start of a frame, the first data byte re-
ceived after the SOF symbol determines the I.D. of
the message frame. This I.D. byte addresses the
I.D. byte flags stored in registers FREG[0:31]. This
operation is accomplished before the transfer of
the I.D. byte into the RXDATA register and before
the RDRF bit is set.
If the corresponding bit in the message filter array,
FREG[0:31], is set to zero (0), then the I.D. byte is
not transferred to the RXDATA register and the
RDRF bit is not set. Also, the remainder of the
message frame is ignored until reception of an
EOFmin symbol. A received EOFmin symbol ter-
minates the operation of the message filter and
enables the receiver for the next message. None
of the flags related to the receiver, other than
IDLE, are set. The EODM flag does not get set
during a filtered frame. No error flags other than
RBRK can get set.
If the corresponding bit in the message filter array,
FREG[0:31], is set to a one (1), then the I.D. byte
is transferred to the RXDATA register and the
RDRF is set. Also, the remainder of the message
is received unless sleep mode is invoked by the
Figure 137. I.D. Byte and Message Filter Array use
294/429
9
Figure
137).
value = n
I.D. byte
user program. All receiver flags and interrupts
function normally.
Note that a break symbol received during a filtered
out message will still be received. Note also that
the filter comparison occurs after reception of the
first byte. So, any receive errors that occur before
the message filter comparison (i.e. IBD, IFD) will
be active at least until the filter comparison.
Transmitted Message Filtering
When transmitting a message, the corresponding
FREG[0:31] I.D. filter bit may be set or cleared. If
set, then the JBLPD will receive all data informa-
tion transferred during the frame, unless sleep
mode is invoked. Everything the JBLPD transmits
will be reflected in the RXDATA register.
Because the JBLPD has invalid bit detect (IBD),
invalid frame detect (IFD), transmitter lost arbitra-
tion (TRA), and Cyclic Redundancy Check Error
(CRCE) it is not necessary for the transmitter to lis-
ten to the bytes that it is transmitting. The user
may wish to filter out the transmitted messages
from the receiver. This can reduce interrupt bur-
den. When a transmitted I.D. byte is filtered by the
receiver section of the block, then RDRF, RDOF,
EODM flags are inhibited and no RXDATA trans-
fers occur. The other flags associated normally
with receiving - RBRK, CRCE, IFD, and IBD - are
not inhibited, and they can be used to ascertain
the condition of the message transmit.
Bit 1 = FREG[0].1
Bit 2 = FREG[0].2
Bit 3 = FREG[0].3
Bit n
Bit n+1
Bit 4 = FREG[0].4
Bit n-1
Bit 254 = FREG[31].6
Bit 255 = FREG[31].7
Bit 0 = FREG[0].0