DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 97

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.1
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority Exception Type
High
Low
2. Not available in this LSI.
Exception Handling Types and Priority
Reset
Trace*
Direct transition*
Interrupt
Trap instruction
executed after execution of an RTE instruction.
Exception Types and Priority
1
Section 4 Exception Handling
2
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on completion
of reset exception handling.
Started by execution of a trap instruction (TRAPA)
Trap instruction exception handling requests are accepted at
all times in program execution state.
Rev.2.00 May. 28, 2009 Page 57 of 732
REJ09B0059-0200