DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 557

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. The operation timings in master receive mode are
shown in figures 17.7 and 17.8. The reception procedure and operations in master receive mode
are shown below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
3. After the reception of one frame data is completed, the RDRF bit in ICSR is set to 1 at the rise
4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time
5. If the next frame is the last receive data, set the RCVD bit in ICCRA to 1 before reading
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stop condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to slave receive mode.
Note: Operation described in step 1 should be executed continuously.
transmit mode to master receive mode. Then, clear the TDRE bit to 0 and read ICDRR
(dummy data read).
and data is received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
of 9th receive clock pulse. At this time, the received data can be read by reading ICDRR and at
the same time the RDRF bit is cleared to 0.
RDRF is set. If the 8th receive clock pulse falls after reading ICDRR by the other processing
while RDRF is 1, SCL is fixed low until ICDRR is read.
ICDRR. This enables the issuance of the stop condition after the next reception.
Master Receive Operation
Rev.2.00 May. 28, 2009 Page 517 of 732
Section 17 I
2
C Bus Interface 3 (IIC3)
REJ09B0059-0200