DF2437FV Renesas Electronics America, DF2437FV Datasheet
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2437 Group 16 Hardware Manual Renesas 16-Bit ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules ...
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This LSI is a microcomputer (MCU) made up of the H8S/2600 CPU with Renesas Technology- original architecture as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general ...
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In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. • In order to understand the detailed function of a register whose name is known Read the index that is the ...
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Main Revisions for This Edition Item Page 12.5.1 Basic Functions 340 Figure 12.8 Periodic Counter Operation 13.3.2 Timer Connection 390 Register O (TCONRO) Table 13.3 HSYNCO Output Selection 16.3.7 Serial Status 453 Register (SSR) Revision (See Manual for Details) Figure ...
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Item Page 16.8.6 SCI Operations 491 during Mode Transitions Figure 16.21 Sample Flowchart for Mode Transition during Transmission All trademarks and registered trademarks are the property of their respective owners. Rev.2.00 May. 28, 2009 Page viii of xxxviii REJ09B0059-0200 Revision ...
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Section 1 Overview........................................................................................... 1 1.1 Features .............................................................................................................................1 1.2 Internal Block Diagram.....................................................................................................2 1.3 Pin Description..................................................................................................................3 1.3.1 Pin Assignment ....................................................................................................3 1.3.2 Pin Assignment in Each Operating Mode............................................................4 1.3.3 Pin Functions .......................................................................................................9 Section 2 CPU................................................................................................... 15 2.1 Features .............................................................................................................................15 2.1.1 Differences between H8S/2600 ...
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Memory Indirect—@@aa:8 ................................................................................ 46 2.7.9 Effective Address Calculation ............................................................................. 46 2.8 Processing States............................................................................................................... 49 2.9 Usage Note........................................................................................................................ 50 2.9.1 Usage Notes on Bit-Wise Operation Instructions ................................................ 50 Section 3 MCU Operating Modes .....................................................................51 3.1 Operating Mode Selection ................................................................................................ 51 ...
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Interrupt Exception Handling Vector Table......................................................................77 5.6 Interrupt Control Modes and Interrupt Operation .............................................................82 5.6.1 Interrupt Control Mode 0 .....................................................................................82 5.6.2 Interrupt Control Mode 2 .....................................................................................84 5.6.3 Interrupt Exception Handling Sequence ..............................................................86 5.6.4 Interrupt Response Times ....................................................................................88 5.7 Usage Notes ...
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Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 143 7.2.5 Pin Functions ....................................................................................................... 143 7.2.6 Port 1 Input Pull-Up MOS States......................................................................... 144 7.3 Port 2................................................................................................................................. 145 7.3.1 Port 2 Data Direction Register (P2DDR)............................................................. 145 7.3.2 Port 2 Data Register (P2DR)................................................................................ ...
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Pin Functions .......................................................................................................189 7.10 Port 9.................................................................................................................................193 7.10.1 Port 9 Data Direction Register (P9DDR).............................................................193 7.10.2 Port 9 Data Register (P9DR)................................................................................194 7.10.3 Port 9 Register (PORT9)......................................................................................194 7.10.4 Port Function Control Register (PFCR) ...............................................................195 7.10.5 Pin Functions .......................................................................................................196 7.11 Port A ................................................................................................................................203 ...
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PWMX (D/A) Counters H and L (DACNTH and DACNTL) ............................. 235 9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB)......................... 236 9.3.3 PWMX (D/A) Control Register (DACR) ............................................................ 238 9.3.4 Peripheral Clock Select Register (PCSR) ............................................................ 239 ...
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Input/Output Pins .............................................................................................................. 278 11.3 Register Descriptions ........................................................................................................280 11.3.1 Timer Counter (TCNT)........................................................................................282 11.3.2 Time Constant Register A (TCORA)...................................................................282 11.3.3 Time Constant Register B (TCORB) ...................................................................282 11.3.4 Timer Control Register (TCR) .............................................................................283 11.3.5 Timer Control/Status Register (TCSR) ................................................................286 11.3.6 Input ...
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Timer I/O Control Register (TIOR) ..................................................................... 320 12.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 329 12.3.5 Timer Status Register (TSR)................................................................................ 331 12.3.6 Timer Counter (TCNT)........................................................................................ 333 12.3.7 Timer General Register (TGR) ............................................................................ 334 12.3.8 Timer Start Register (TSTR) ............................................................................... ...
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HSYNCO Output .................................................................................................414 13.4.8 VSYNCO Output .................................................................................................415 13.4.9 CBLANK Output .................................................................................................416 Section 14 Duty Measurement Circuit.............................................................. 417 14.1 Features .............................................................................................................................417 14.2 Input/Output Pins .............................................................................................................. 419 14.3 Register Descriptions ........................................................................................................420 14.3.1 Free-Running Counter (TWCNT)........................................................................420 14.3.2 Input Capture Register (TWICR).........................................................................420 14.3.3 ...
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Changing Values of CKS2 to CKS0 Bits............................................................. 443 15.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 443 Section 16 Serial Communication Interface (SCI) ............................................445 16.1 Features............................................................................................................................. 445 16.2 Input/Output Pins .............................................................................................................. 447 16.3 Register Descriptions ........................................................................................................ 448 ...
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SCI Operations during Mode Transitions ............................................................491 16.8.7 Switching from SCK Pins to Port Pins ................................................................494 2 Section Bus Interface 3 (IIC3) ............................................................... 497 17.1 Features .............................................................................................................................497 17.2 Input/Output Pins .............................................................................................................. 500 17.3 Register Descriptions ........................................................................................................500 2 ...
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External Trigger Input Timing............................................................................. 541 18.5 Interrupt Source ................................................................................................................ 542 18.6 A/D Conversion Accuracy Definitions ............................................................................. 542 18.7 Usage Notes ...................................................................................................................... 544 18.7.1 Module Stop Mode Setting .................................................................................. 544 18.7.2 Permissible Signal Source Impedance ................................................................. 544 18.7.3 Influences on ...
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Connecting Crystal Resonator .............................................................................640 21.2.2 External Clock Input Method...............................................................................641 21.3 Duty Adjustment Circuit ...................................................................................................643 21.4 Divider ..............................................................................................................................643 21.5 Usage Notes ......................................................................................................................644 21.5.1 Note on Resonator................................................................................................644 21.5.2 Notes on Board Design ........................................................................................644 21.5.3 Notes on Operation Confirmation........................................................................644 Section 22 Power-Down ...
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A/D Conversion Characteristics........................................................................................ 720 24.5 Flash Memory Characteristics .......................................................................................... 721 24.6 Usage Notes ...................................................................................................................... 722 Appendix .........................................................................................................723 A. I/O Port States in Each Pin State....................................................................................... 723 B. Product Lineup.................................................................................................................. 725 C. Package Dimensions ......................................................................................................... 726 Index .........................................................................................................727 Rev.2.00 May. ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2437 Group .......................................................2 Figure 1.2 Pin Assignment of H8S/2437 Group (FP-128B)..................................................3 Figure 1.3 Sample Design of Reset Signals without Affection Each Other ..........................14 Section 2 CPU Figure 2.1 Exception-Handling Vector Table ...
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Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)........................ 104 Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space)...................... 105 Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space........................................................ 107 Figure 6.6 Bus Timing for 8-Bit, ...
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Figure 9.4 Output Waveform ( DADR Corresponds to T Figure 9.5 D/A Data Register Configuration when CFS = 1.................................................244 Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1)............................................245 Section 10 16-Bit Free-Running Timer (FRT) Figure 10.1 ...
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Figure 11.14 Conflict between TCNT Write and Increment..................................................... 304 Figure 11.15 Conflict between TCOR Write and Compare-Match........................................... 305 Section 12 16-Bit Timer Pulse Unit (TPU) Figure 12.1 Block Diagram of TPU ........................................................................................ 310 16-Bit Register Access Operation [Bus Master ↔ ...
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Figure 12.39 Buffer Operation Timing (Compare Match) ........................................................366 Figure 12.40 Buffer Operation Timing (Input Capture)............................................................366 Figure 12.41 TGI Interrupt Timing (Compare Match)..............................................................367 Figure 12.42 TGI Interrupt Timing (Input Capture)..................................................................368 Figure 12.43 TCIV Interrupt Setting Timing ............................................................................369 Figure 12.44 TCIU Interrupt ...
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Figure 14.5 Count Start Timing for Duty Measurement ......................................................... 426 Figure 14.6 Input Capture Timing during Duty Measurement................................................ 426 Figure 14.7 Clear Timing for START Bit when Duty Measurement Ends............................. 427 Figure 14.8 Set Timing for Duty Measurement End Flag ...
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Figure 16.18 Example of SCI Receive Operation in Clocked Synchronous Mode...................484 Figure 16.19 Sample Serial Reception Flowchart .....................................................................485 Figure 16.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............487 Figure 16.21 Sample Flowchart for Mode Transition during Transmission .............................491 Figure ...
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Figure 20.4 Block Division of User MAT............................................................................... 554 Figure 20.5 Overview of User Procedure Program ................................................................. 555 Figure 20.6 System Configuration in Boot Mode ................................................................... 576 Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI.............................................. 576 Figure 20.8 Overview of State Transition ...
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Figure 24.8 Basic Bus Timing/2-State Access ........................................................................707 Figure 24.9 Basic Bus Timing/3-State Access ........................................................................708 Figure 24.10 Basic Bus Timing/3-State Access with One Wait State.......................................709 Figure 24.11 Muliplex Bus Timing/2-State Access ..................................................................711 Figure 24.12 Multiplex Bus Timing/3-State Access .................................................................712 Figure 24.13 ...
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Rev.2.00 May. 28, 2009 Page xxxii of xxxviii REJ09B0059-0200 ...
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Section 1 Overview Table 1.1 Pin Assignment in Each Operating Mode............................................................4 Table 1.2 Pin Functions .......................................................................................................9 Section 2 CPU Table 2.1 Instruction Classification .....................................................................................31 Table 2.2 Operation Notation...............................................................................................32 Table 2.3 Data Transfer Instructions....................................................................................33 Table 2.4 Arithmetic Operations Instructions (1) ................................................................34 ...
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Table 6.3 Bus Specifications for Normal Extended Bus Interface....................................... 100 Table 6.4 Address Range and External Address Area (Multiplex Extended Mode)............ 101 Table 6.5 Bus Specifications for Multiplex Extended Bus Interface (Address Cycle) ........ 101 Table 6.6 Bus Specifications for ...
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Table 11.4 Timer Output Priorities ........................................................................................306 Table 11.5 Switching of Internal Clocks and TCNT Operation.............................................307 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.1 TPU Functions .....................................................................................................311 Table 12.2 Pin Configuration.................................................................................................313 Table 12.3 CCLR2 to CCLR0 (Channel 0)............................................................................316 Table 12.4 ...
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Table 13.12 VSYNCO Output Modes ..................................................................................... 415 Section 14 Duty Measurement Circuit Table 14.1 Pin Configuration................................................................................................. 419 Table 14.2 Interrupt Sources for Duty Measurement Circuit................................................. 428 Table 14.3 Switching of Internal Clock and TWCNT Operation .......................................... 431 Table 14.4 Switching ...
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Table 20.4 Parameters and Target Modes..............................................................................566 Table 20.5 Setting On-Board Programming Mode ................................................................575 Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment............................577 Table 20.7 Executable MAT..................................................................................................594 Table 20.8 (1) Usable Area for Programming in User Program Mode........................................595 Table 20.8 (2) Usable ...
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Rev.2.00 May. 28, 2009 Page xxxviii of xxxviii REJ09B0059-0200 ...
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Features • High-speed H8S/2600 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 69 basic instructions Multiply-and-accumulate instruction • Various peripheral functions 8-bit PWM timer (PWM) ...
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Internal Block Diagram Figure 1.1 shows the internal block diagram of the H8S/2437 Group. P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12/ P05/AN13/ P06/AN14/ P07/AN15/ P10/PW0/A0/AD0 P11/PW1/A1/AD1 P12/PW2/A2/AD2 P13/PW3/A3/AD3 P14/PW4/A4/AD4 P15/PW5/A5/AD5 P16/PW6/A6/AD6 P17/PW7/A7/AD7 P20/TIOCA0/A8/AD8 P21/TIOCB0/A9/AD9 P22/TIOCC0/TCLKA/A10/AD10 P23/TIOCD0/TCLKB/A11/AD11 P24/TIOCA1/A12/AD12 P25/TIOCB1/TCLKC/A13/AD13 P26/TIOCA2/A14/AD14 P27/TIOCB2/TCLKD/A15/AD15 P30/ ...
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Pin Description 1.3.1 Pin Assignment Figure 1.2 shows the pin assignment of the H8S/2437 Group. PC0/SCL2 103 PC1/SDA2 104 PC2/SCL3 105 PC3/SDA3 106 P27/TIOCB2/TCLKD/A15/AD15 107 P26/TIOCA2/A14/AD14 108 P25/TIOCB1/TCLKC/A13/AD13 109 P24/TIOCA1/A12/AD12 110 P23/TIOCD0/TCLKB/A11/AD11 111 P22/TIOCC0/TCLKA/A10/AD10 112 P21/TIOCB0/A9/AD9 113 P20/TIOCA0/A8/AD8 114 ...
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Pin Assignment in Each Operating Mode Table 1.1 Pin Assignment in Each Operating Mode Pin No. Extended Mode (EXPE = 1) QFP- 128 Normal Multiplex 1 D11 P33/ExIRQ3 2 D10 P32/ExIRQ2 3 D9 P31/ExIRQ1 4 D8 P30/ExIRQ0 5 D7 ...
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Pin No. Extended Mode (EXPE = 1) QFP- 128 Normal Multiplex RES 28 29 VSS 30 VCL 31 VCC 32 EXTAL 33 XTAL 34 VSS 35 ETMS/PC4* 36 ETCK/PC5* STBY 37 38 ETDI/PC6* ETRST 39 40 ETDO/PC7* 41 P50/SCK0 42 ...
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Pin No. Extended Mode (EXPE = 1) QFP- 128 Normal Multiplex 58 P73/AN3 59 P74/AN4 60 P75/AN5 61 P75/AN6 62 P77/AN7 63 P00/AN8 64 P01/AN9 65 P02/AN10 66 P03/AN11 67 P04/AN12/ExIRQ4 68 P05/AN13/ExIRQ5 69 P06/AN14/ExIRQ6 70 P07/AN15/ExIRQ7 71 AVCC 72 ...
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Pin No. Extended Mode (EXPE = 1) QFP- 128 Normal Multiplex 88 P86/ExTIOCA0 89 P85/PWX1 90 P84/PWX0 91 PA7/CS3/ExTIOCA1 92 PA6/FTCI_0/HFBACKI 93 PA5/FTIB_0/VFBACKI 94 PA4/FTIC_0/CLAMPO 95 PA3/FTOB_0/CBLANK 96 PA2/TMO0_0/ExTIOCC0/ ExTCLKA 97 PA1/TMOY_0/ExPW7/SCK4 98 PA0/TMOX_0/ExPW6/SCK3 99 P83/SDA1/RxD4 100 P82/SCL1/TxD4 101 P81/SDA0/RxD3 ...
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Pin No. Extended Mode (EXPE = 1) QFP- 128 Normal Multiplex 118 VSS 119 P15/A5 AD5 120 P14/A4 AD4 121 P13/A3 AD3 122 P12/A2 AD2 123 P11/A1 AD1 124 P10/A0 AD0 125 D15 P37 126 D14 P36 127 D13 P35 ...
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Pin Functions Table 1.2 Pin Functions Type Symbol Power VCC supply VCL VSS Clock XTAL EXTAL φ Operating MD2 mode control MD1 MD0 RES System control STBY FWE Address bus A15 Data bus D15 ...
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Type Symbol WAIT Bus control RD HWR LWR AS CS3 to CS1 AH Interrupts NMI IRQ7 to IRQ0 ExIRQ7 to ExIRQ0 ETRST* 2 On-chip emulator ETMS ETDO ETDI ETCK 8-bit PWM PW7 to PW0 timer (PWM) ExPW7 ...
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Type Symbol 14-bit PWM PWX0 timer PWX1 (PWMX) 16-bit free- FTCI_0 running FTCI_1 timer (FRT) FTOA_0 FTOA_1 FTOB_0 FTOB_1 FTIA_0 to FTID_0 FTIA_1 to FTID_1 8-bit timer TMO0_0 (TMR0, TMO0_1 TMR1, TMO1_0 TMRX, TMO1_1 TMRY) TMOX_0 TMOX_1 TMOY_0 TMOY_1 TMI0_0 ...
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Type Symbol 16-bit timer TCLKA to pulse unit TCLKD (TPU) ExTCLKA to ExTCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 ExTIOCA0 ExTIOCB0 ExTIOCC0 ExTIOCD0 TIOCA1 TIOCB1 ExTIOCA1 ExTIOCB1 TIOCA2 TIOCB2 ExTIOCA2 ExTIOCB2 Timer VSYNCI_0 connection VSYNCI_1 HSYNCI_0 HSYNCI_1 CSYNCI_0 CSYNCI_1 HFBACKI VFBACKI VSYNCO ...
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Type Symbol bus SCL0, SCL1 interface 3 SCL2, SCL3 (IIC3) SDA0, SDA1 SDA2, SDA3 A/D AN15 to AN0 converter ADTRG AVCC AVref AVSS I/O ports P07 to P00 P17 to P10 P27 to P20 P37 to P30 ...
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Notes: 1. Not supported by the on-chip emulator. 2. Following precautions are required on the power-on reset signal that is applied to the ETRST pin. The reset signal must be applied at a power-on. Apart the power-on reset circuit from ...
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The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Two CPU operating modes Normal mode* Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: Normal mode ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. ...
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Higher speed Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. ...
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Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as ...
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Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers the upper 16-bit segments of 32-bit ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a ...
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Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The ...
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Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended register (EXR), an 8-bit condition ...
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General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by ...
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Bit Bit Name Initial Value R Undefined 0 C Undefined 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of ...
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Data Formats The H8S/2600 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
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Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made ...
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Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* LDM, STM MOVFPE* Arithmetic ADD, SUB, CMP, ...
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Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General register (destination)* Rs ...
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Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Transfers data between two general registers or between a general register and memory, or transfers immediate data to a general register. MOVFPE B Cannot ...
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Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and data in a ...
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Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers. Either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 ...
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Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → ...
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Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Table 2.7 Bit Manipulation Instructions (2) 1 Instruction Size* BXOR B BIXOR B BLD B BILD B BST B BIST B Note: Size refers to the operand size. B: Byte Rev.2.00 May. 28, 2009 Page 38 of 732 REJ09B0059-0200 Function ...
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Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC B/W Transfers the ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — else next ≠ 0 then EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
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Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. ...
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Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. ...
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Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum gives the address ...
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Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: * Not available in this LSI. 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The instruction code ...
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Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address ...
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Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Register direct (Rn) Register indirect (@ERn) Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ •Register indirect with pre-decrement @-ERn Effective Address Calculation General register contents General ...
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Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: Normal mode is not available in this LSI. * Rev.2.00 May. 28, 2009 Page 48 of 732 REJ09B0059-0200 Effective Address Calculation PC contents Sign extension ...
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Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The CPU and on-chip peripheral ...
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Bus-released state Exception handling state = High *1 Reset state Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever A transition can also be made to the reset state when ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has four operating modes (modes and 7). These modes are determined by the mode pin settings (MD2, MD1, and MD0). For normal program execution mode, the ...
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Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode and operating mode settings. Bit Bit Name ...
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System Control Register (SYSCR) SYSCR selects saturating calculation for the MAC instruction, and controls reset source monitor, Ram address space, and on-chip flash memory control. Bit Bit Name Initial Value 7 MACS 0 ⎯ All 0 ...
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Operating Mode Descriptions 3.3.1 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The initial mode after a reset is single-chip mode, to use the external address space, set the ...
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Pin Functions The pin functions of ports and A change according to operating modes. Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Normal Extended ...
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Memory Map Figure 3.1 shows a memory map. ROM : 256 kbytes, RAM : 16 kbytes Mode 7 (EXPE = 1) Advanced mode External mode with on-chip ROM enabled H'000000 H'03FFFF H'040000 H'07FFFF H'080000 H'FBFFFF H'FC0000 H'FCFFFF H'FD0000 H'FDFFFF ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more ...
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Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, ...
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Exception Source 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. Not available in this LSI. Becomes reserved for system use. 4. For details on internal interrupt vectors, see section 5.5, ...
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Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception-handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception-handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction 4.3.2 ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values ...
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Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes (b) Advanced Modes Notes: 1. Ignored on return. 2. Normal modes are not available in ...
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Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word size or longword size and the value of the stack pointer (SP, ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An ...
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A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 INTCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt sources WOVI to IICI3 Interrupt controller [Legend] ISCR: IRQ sense control ...
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Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ7 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
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Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value ⎯ ⎯ 5 INTM1 0 4 INTM0 0 3 NMIEG ...
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Interrupt Priority Registers (IPRA to IPRK) IPR are eleven 16-bit readable/writable registers that set priorities (levels for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table ...
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Bit Bit Name Initial Value R/W 6 IPR6 1 5 IPR5 1 4 IPR4 1 ⎯ IPR2 1 1 IPR1 1 0 IPR0 1 Rev.2.00 May. 28, 2009 Page 70 of 732 REJ09B0059-0200 Description R/W Sets the ...
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IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value R/W 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 ...
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IRQ Sense Control Registers (ISCR) ISCR select the source that generates an interrupt request at pins IRQ7 to IRQ0. Bit Bit Name Initial Value R/W 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB 0 12 IRQ6SCA 0 11 IRQ5SCB ...
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Bit Bit Name Initial Value R/W 9 IRQ4SCB 0 8 IRQ4SCA 0 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 Description R/W IRQ4 Sense Control B R/W IRQ4 Sense Control A 00: Interrupt request generated at ...
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Bit Bit Name Initial Value R/W 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 Rev.2.00 May. 28, 2009 Page 74 of 732 REJ09B0059-0200 Description R/W IRQ1 Sense Control B R/W IRQ1 Sense Control A 00: Interrupt ...
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IRQ Status Register (ISR) ISR is an IRQ7 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value R/W 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 ...
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Interrupt Sources 5.4.1 External Interrupt Sources There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, ...
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A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2. IRQnSCA, IRQnSCB Edge/ level detection circuit input Note Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 5.4.2 Internal Interrupts The sources ...
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Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Vector Source Source Number External NMI 7 pin IRQ0 16 IRQ1 17 IRQ2 18 IRQ3 19 IRQ4 20 IRQ5 21 IRQ6 22 IRQ7 23 ⎯ Reserved for ...
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Origin of Interrupt Interrupt Vector Source Source Number ⎯ Reserved for 44 system use 45 A/D ADI 46 TPU_0 TGI0A 47 TGI0B 48 TGI0C 49 TCI0D 50 TCI0V 51 TPU_1 TGI1A 52 TGI1B 53 TCI1V 54 TCI1U 55 TPU_2 TGI2A ...
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Origin of Interrupt Interrupt Vector Source Source Number TMR1_0 CMIA10 74 CMIB10 75 OVI10 76 TMRY_0 CMIAY0 77 CMIBY0 78 OVIY0 79 TMRX_1 CMIAX1 80 CMIBX1 81 OVIX1 82 ICIX1 83 FRT_1 ICIA1 84 ICIB1 85 ICIC1 86 ICID1 87 ...
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Origin of Interrupt Interrupt Vector Source Source Number SCI_0 ERI0 102 RXI0 103 TXI0 104 TEI0 105 SCI_1 ERI1 106 RXI1 107 TXI1 108 TEI1 109 SCI_2 ERI2 110 RXI2 111 TXI2 112 TEI2 113 SCI_3 ERI3 114 RXI3 115 ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table ...
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The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure 5.3 Flowchart of Procedure ...
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Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level ( bits) in the CPU and the IPR ...
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Program execution status Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address ...
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Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Figure 5.5 Interrupt Exception Handling Rev.2.00 May. 28, 2009 Page 87 of 732 REJ09B0059-0200 ...
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Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained ...
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Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch S I Branch address read S J Stack manipulation S K [Legend] m: Number of wait states in an external device access. Object of Access 8 ...
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Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared by an instruction such ...
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Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is ...
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IRQ Pin Select 5.7.5 IRQ input pins can be selected from port control register 1 (PTCNT1). For details on selectable pins, refer to section 7, I/O Ports. When the PTCNT1 setting is changed, an edge occurs internally and the IRQnF ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. 6.1 Features • Extended modes Two modes for external extension Normal ...
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Multiplex Extension: The address output pins and data input/output pins are multiplex pins • Minimization of number of pins It is possible to minimize the number of pins necessary for expansion by multiplexing the address output pins and data input/output ...
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Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Symbol I/O Function AS Output Strobe signal indicating that address output on address bus is enabled, during normal expansion CS1 Output Chip select ...
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Register Descriptions Registers related to the bus controller are as follows. • Bus control register (BCR) • Basic area/area 1 control register (BCRA1) • Area 2 control register (BCRA2) • Area 3 control register (BCRA3) 6.3.1 Bus Control Register ...
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Initial Bit Bit Name Value 0 ADMXE 0 6.3.2 Area Control Register (BCRA) BCRA designates the access mode in area 1 to area 3. The basic area indicates the setting of area 1. Initial Bit Bit Name Value 7 ABWn ...
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Initial Bit Bit Name Value 4 AWn 1 3 WMSn1 0 2 WMSn0 0 1 WCn1 1 0 WCn0 1 [Legend Rev.2.00 May. 28, 2009 Page 98 of 732 REJ09B0059-0200 R/W Description R/W Multiplex Extended ...
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Bus Control 6.4.1 Bus Specifications The external address space bus specifications consist of three elements: bus width, number of access states, and the number of wait modes and program wait states. The bus width and number of access states ...
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Table 6.3 Bus Specifications for Normal Extended Bus Interface ASTn WMSn1 ⎯ [Legend Don’t care. Multiplex Extended Mode: The bus access is used as both the address bus and ...
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The external extended wait function is effective when the low-speed device is connected to the external address area. For details on multiplex extended address range, external address area, as well as bus interface specifications, refer to tables 6.4 to 6.6. ...
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External Address Area The initial condition of the external address space is normal extended 3-state access space. The space outside the on-chip ROM, on-chip RAM, internal I/O register, and their reserved areas are available as the external address spaces. ...
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Address Strobe/Hold Signal In normal extended mode, the address above the bus address is enabled, which is indicated by the output strobe signal (AS). In multiplex extended mode, the hold signal (AH) which indicates the address fetch timing, is ...
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Bus Interface The normal extended bus interface enables direct connection between the ROM and SRAM. For details on the basic area and areas bus specification selection, refer to tables 6.2 and 6.3. For multiplex extended bus ...
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Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8/AD15 to AD8) and lower data bus (D7 to D0/AD7 to AD0) are used for ...
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Valid Strobes Table 6.7 shows the data buses used and valid strobes for each access space read, the RD signal is valid for both the upper and lower halves of the data bus write, the ...
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Basic Operation Timing in Normal Extended Mode 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data ...
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Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. ...
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Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and ...
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Address bus D15 to D8 Read Write D15 Note Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) Rev.2.00 May. 28, 2009 Page 110 ...
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Address bus D15 to D8 Read Write D15 Note Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Bus cycle Valid ...
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Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and ...
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Address bus D15 to D8 Read Write D15 Note Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Bus cycle ...
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Address bus D15 to D8 Read Write D15 Note Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev.2.00 May. 28, 2009 Page 114 of ...
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Basic Operation Timing in Multiplex Extended Mode 8-Bit, 2-State Data Access Space: Figures 6.13 and 6.14 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) ...
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AD15 to AD8 Note Figure 6.14 Bus Timing for 8-Bit, 2-State Data Access Space (Without Address Wait) Rev.2.00 May. 28, 2009 Page 116 of 732 REJ09B0059-0200 Read Cycle Address Data ...
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Data Access Space: Figure 6.15 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the address bus and the data bus are used. ...
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Data Access Space: Figures 6.16 to 6.21 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the address bus uses all buses (AD15 to AD0), the upper half (AD15 to AD8) ...
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Read Cycle Address AD15 to AD8 Address AD7 to AD0 Address Note Figure 6.17 Bus Timing for 16-Bit, 2-State Data Access Space (2) (Even Byte Access, without Address Wait) Write Cycle ...
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AD15 to AD8 AD7 to AD0 Note Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3) Rev.2.00 May. 28, 2009 Page 120 of 732 REJ09B0059-0200 Read Cycle Address Data ...
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Read Cycle Address AD15 to AD8 Address Address AD7 to AD0 Note Figure 6.19 Bus Timing for 16-Bit, 2-State Data Access Space (4) (Odd Byte Access, without Address Wait) Write Cycle ...
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AD15 to AD8 AD7 to AD0 Note Figure 6.20 Bus Timing for 16-Bit, 2-State Data Access Space (5) Rev.2.00 May. 28, 2009 Page 122 of 732 REJ09B0059-0200 Read Cycle Address Data ...
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Read Cycle Address Address AD15 to AD8 AD7 to AD0 Address Note Figure 6.21 Bus Timing for 16-Bit, 2-State Data Access Space (6) (Word Access, without Address Wait) Write Cycle Data ...
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Data Access Space: Figures 6.22 to 6.24 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the address bus uses all buses (AD15 to AD0), the upper half (AD15 to AD8) ...
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Address AD15 to AD8 Address AD7 to AD0 Address Note Figure 6.23 Bus Timing for 16-Bit, 3-State Data Access Space (2) Read Cycle Data ...
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Address AD15 to AD8 Address AD7 to AD0 Address Note Figure 6.24 Bus Timing for 16-Bit, 3-State Data Access Space (3) Rev.2.00 May. 28, 2009 Page 126 of 732 REJ09B0059-0200 Read ...
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Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting the wait states (T ). Ways of inserting wait states: Program wait insertion, pin wait insertion using the W WAIT pin, and ...
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Address bus Read Data bus Write Data bus Notes: 1. Downward arrows indicate the timing Figure 6.25 Example of Wait State Insertion Timing (Normal Extended Pin Wait Mode) In Multiplex Extended Mode: 1. ...
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Pin Wait Mode When accessing the external address space, a specified number of wait states T inserted between the T state and T 4 edge of φ in the last states are inserted until ...
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Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (T bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for ...
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Table 6.8 shows the pin states in an idle cycle. Table 6.8 Pin States in Idle Cycle Pins A15 to A0 D15 to D0 AD15 to AD0 AS/AH CSn RD HWR, LWR [Legend Pin State ...
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Rev.2.00 May. 28, 2009 Page 132 of 732 REJ09B0059-0200 ...
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Table 7 summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output, a data ...
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Table 7.1 Port Functions (1) Extended Mode (EXPE = 1) Port Description Normal Port 0 General input P07/AN15/ExIRQ7 port also P06/AN14/ExIRQ6 functioning as P05/AN13/ExIRQ5 an A/D converter P04/AN12/ExIRQ4 analog input P03/AN11 and interrupt P02/AN10 input. P01/AN9 P00/AN8 Port 1 General ...
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Table 7.1 Port Functions (2) Port Description Normal Port 3 General I/O D15 port also D14 functioning as D13 a bidirectional data bus and D12 interrupt input. D11 D10 D9 D8 Port 4 General I/O P47/IRQ7/TMIY_0/ExPW3 port also P46/IRQ6/TMIX_0/ExPW2 functioning ...
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Table 7.1 Port Functions (3) Extended Mode (EXPE = 1) Port Description Normal Port 6 General I/O port D7* also functioning D6 D5* bidirectional data bus, D4* FRT_1 D3* input/output, D2* TMRX_1 and TMRY_1 D1* output, and D0* ...
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Table 7.1 Port Functions (4) Extended Mode (EXPE = 1) Port Description Normal Port 8 General I/O P87/ADTRG/ExTIOCB0 port also P86/ExTIOCA0 functioning as P85/PWX1 an A/D converter P84/PWX0 external P83/SDA1/RxD4 trigger input, P82/SCL1/TxD4 PWMX output, SCI_3, SCI_4, P81/SDA0/RxD3 IIC3_0, and ...
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Table 7.1 Port Functions (5) Extended Mode (EXPE = 1) Port Description Normal Port A PA7/CS3/ExTIOCA1 General I/O port also functioning PA6/FTCI_0/HFBACKI as a bus control PA5/FTIB_0/VFBACKI output, FRT_0 input/output, PA4/FTIC_0/CLAMPO TMX_0, TMY_0, PA3/FTOB_0/CBLANK and TM0_0 PA2/TMO0_0/ExTIOCC0/ExTCLKA output, timer PA1/TMOY_0/ExPW7/SCK4 ...
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Port 0 Port 8-bit input port. Port 0 pins also function as A/D converter analog input pins and EXIRQ input pins. Port 0 has the following register. • Port 0 register (PORT0) 7.1.1 Port 0 Register ...
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P07/AN15/ExIRQ7 Pin P07 input pin function AN15 input pin/ExIRQ7 input pin* * When the IRQ7S bit in PTCNT1 is set functions as the ExIRQ7 input. Note: • P06/AN14/ExIRQ6 Pin P06 input pin function AN14 input pin/ExIRQ6 ...
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P00/AN8 Pin P00 input pin function AN8 input pin 7.2 Port 1 Port 8-bit I/O port. Port 1 pins also function as address bus pins, address/data multiplex bus pins, and PWM output pins. Pin functions change ...
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Port 1 Data Register (P1DR) P1DR stores output data for port 1. Bit Bit Name Initial Value 7 P17DR 0 6 P16DR 0 5 P15DR 0 4 P14DR 0 3 P13DR 0 2 P12DR 0 1 P11DR 0 0 ...
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Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on or off state of input pull-up MOSs for port 1. Bit Bit Name Initial Value 7 P17PCR 0 6 P16PCR 0 5 P15PCR 0 4 P14PCR 0 3 ...
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Single-Chip Mode (EXPE = 0) P1nDDR 0 ⎯ PWnS ⎯ OEn Pin function P1n input pin [Legend 7.2.6 Port 1 Input Pull-Up MOS States Port 1 has an on-chip input pull-up MOS that can ...
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Port 2 Port 8-bit I/O port. Port 2 pins also function as address bus pins, address/data multiplex bus pins, and TPU I/O pins. Pin functions change according to the operating mode. Port 2 has the following ...
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Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value 7 P27DR 0 6 P26DR 0 5 P25DR 0 4 P24DR 0 3 P23DR 0 2 P22DR 0 1 P21DR ...
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Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the on or off state of input pull-up MOSs for port 2. Bit Bit Name Initial Value 7 P27PCR 0 6 P26PCR 0 5 P25PCR 0 4 P24PCR 0 3 ...
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Single-Chip Mode (EXPE = 0) TIOCB2/ TCLKDS TPU channel Table below (2) 2 setting P27DDR 0 Pin function P27 input pin TIOCB2 input pin* TPU channel (2) 2 setting MD3 to MD0 B'0000, B'01xx IOB3 to IOB0 B'0000 B'0100 ...
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Extended Mode (EXPE = 1) Normal Extended Mode (ADMXE = 0) P26DDR 0 Pin function P26 input pin • Single-Chip Mode (EXPE = 0) TIOCA2S TPU channel Table below (2) 2 setting P26DDR 0 Pin function P26 input pin ...
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Extended Mode (EXPE = 1) Normal Extended Mode (ADMXE = 0) P25DDR 0 Pin function P25 input pin • Single-Chip Mode (EXPE = 0) TIOCB1/ TCLKCS TPU channel 1 Table below (2) setting P25DDR 0 Pin function P25 input ...
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P24/TIOCA1/A12/AD12 When the TIOCA1S bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCA1 pin. According to operating modes, the TPU channel 1 settings by the MD3 to MD0 bits in TMDR_1, the IOA3 ...
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P23/TIOCD0/TCLKB/A11/AD11 When the TIOCD0/TCLKBS bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCD0/TCLKB pin. According to operating modes, the TPU channel 0 settings by the MD3 to MD0 bits in TMDR_0, the IOD3 ...
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Don’t care Notes: 1. When TIOCD0/TCLKBS = 0, MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx, this pin functions as the TIOCD0 input pin. 2. When TIOCD0/TCLKBS = 0 and TPSC2 to TPSC0 in one ...
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TPU channel (2) 0 setting MD3 to MD0 B'0000 IOC3 to IOC0 B'0000 B'0100 B'1xxx ⎯ CCLR2 to CCLR0 ⎯ Output function [Legend] x: Don’t care Notes: 1. When TIOCC0/TCLKAS = 0, MD3 to MD0 = B'0000, and IOC3 to ...
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Single-Chip Mode (EXPE = 0) TIOCB0S TPU channel Table below (2) 0 setting P21DDR 0 Pin function P21 input pin TIOCB0 input pin* TPU channel (2) 0 setting MD3 to MD0 IOB3 to IOB0 B'0000 B'0100 B'1xxx ⎯ CCLR2 ...
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Single-Chip Mode (EXPE = 0) TIOCA0S TPU channel Table below (2) 0 setting P20DDR 0 Pin function P20 input pin TIOCA0 input pin* TPU channel (2) 0 setting MD3 to MD0 IOA3 to IOA0 B'0000 B'0100 B'1xxx ⎯ CCLR2 ...
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Port 2 Input Pull-Up MOS States Port 2 has an on-chip input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode. Table 7.3 summarizes the input pull-up MOS ...
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Port 3 Port 8-bit I/O port. Port 3 pins also function as bidirectional data bus and ExIRQ input pins. Port 3 functions change according to the operating mode. Port 3 has the following registers. • Port ...
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Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value 7 P37DR 0 6 P36DR 0 5 P35DR 0 4 P34DR 0 3 P33DR 0 2 P32DR 0 1 P31DR ...
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Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the on or off state of input pull-up MOSs for port 3. Bit Bit Name Initial Value 7 P37PCR 0 6 P36PCR 0 5 P35PCR 0 4 P34PCR 0 3 ...