DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 66

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
7
6
5
4
3
2
Rev.2.00 May. 28, 2009 Page 26 of 732
REJ09B0059-0200
Condition-Code Register (CCR)
Bit Name
I
UI
H
U
N
Z
Initial Value R/W
1
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 by hardware at the start of an exception-handling
sequence. For details, refer to section 5, Interrupt
Controller.
User Bit or Interrupt Mask Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit
cannot be used as an interrupt mask bit in this LSI.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or
NEG.L instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to 0
otherwise.
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.