DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 579

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3. When conversion for all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not cleared automatically, and steps 2 and 3 are repeated as long as the ADST
18.4.3
The A/D converter has an on-chip sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
then starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D
conversion time.
As shown in figure 18.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in tables 18.3.
In scan mode, the values given in tables 18.3 apply to the first conversion time. The values given
in table 18.4 apply to the second and subsequent conversions.
SPL
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. Conversion for
the first channel in the channel set starts again.
bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D
converter enters the wait state. Then if the ADST bit is set to 1, A/D conversion starts again for
the first channel in the channel set.
). The length of t
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total
D
) passes after the ADST bit in ADCSR is set to 1,
CONV
) includes t
Rev.2.00 May. 28, 2009 Page 539 of 732
D
and the input sampling time
REJ09B0059-0200