DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 58
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
DF2437FV
Manufacturer:
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Quantity:
10 000
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• Higher speed
2.2
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1
The exception-handling vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
• Extended Registers (En)
• Instruction Set
• Exception-handling Vector Table and Memory Indirect Branch Addresses
Rev.2.00 May. 28, 2009 Page 18 of 732
REJ09B0059-0200
Basic instructions execute twice as fast.
The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space.
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When En is used as a 16-bit register it can contain any value, even when the corresponding
general register (Rn) is used as an address register. If the general register is referenced in the
register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a
carry or borrow occurs, however, the value in the corresponding extended register (En) will be
affected.
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
In normal mode the top area starting at H'0000 is allocated to the exception-handling vector
table. One branch address is stored per 16 bits. The exception-handling vector table in normal
mode is shown in figure 2.1. For details of the exception-handling vector table, see section 4,
Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception-handling vector table.
CPU Operating Modes
Normal Mode
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