DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 504
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. If receive data is sampled at the rising edge of the 8th pulse of the basic
clock, data is latched at the middle of each bit, as shown in figure 16.3. Thus the reception margin
in asynchronous mode is determined by formula (1) below.
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
M = {0.5 – 1/(2 × 16)} × 100
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Rev.2.00 May. 28, 2009 Page 464 of 732
REJ09B0059-0200
M = (0.5 –
}
M: Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
2N
1
Figure 16.3 Receive Data Sampling Timing in Asynchronous Mode
) –
D – 0.5
N
0
[%] = 46.875 %
8 clocks
Start bit
– (L – 0.5) F } × 100
16 clocks
7
[%]
15 0
... Formula (1)
D0
7
15 0
D1
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