DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 74

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 2.4
Note:
Rev.2.00 May. 28, 2009 Page 34 of 732
REJ09B0059-0200
Instruction
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU
MULXS
DIVXU
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Arithmetic Operations Instructions (1)
Size*
B/W/L
B
B/W/L
L
B
B/W
B/W
B/W
Function
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data cannot
be subtracted from byte data in a general register. Use the SUBX or ADD
instruction.)
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in two
general registers, or on immediate data and data in a general register.
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands can
be incremented or decremented by 1 only)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers.
Either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs signed multiplication on data in two general registers.
Either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers.
Either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or
32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.