DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 322

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3.1
TCNT is an 8-bit readable/writable up-counter. TCNT0 and TCNT1 (or TCNTY and TCNTX)
comprise a single 16-bit register, so they can be accessed together in word units. The clock source
is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input
signal, compare-match A signal, or compare-match B signal. The method of clearing can be
selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to
H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00.
11.3.2
TCORA is an 8-bit readable/writable register. TCORA0 and TCORA1 (or TCORAY and
TCORAX) comprise a single 16-bit register, so they can be accessed together in word units.
TCORA is continually compared with the value in TCNT. When a match is detected, the CMFA
flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a
TCORA write cycle. The timer output from the TMO pin can be freely controlled by this
compare-match A signal and the settings of the OS1 and OS0 bits in TCSR. TCORA is initialized
to H'FF.
11.3.3
TCORB is an 8-bit readable/writable register. TCORB0 and TCORB1 (or TCORBY and
TCORBX) comprise a single 16-bit register, so they can be accessed together in word units.
TCORB is continually compared with the value in TCNT. When a match is detected, the CMFB
flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a
TCORB write cycle. The timer output from the TMO pin can be freely controlled by this compare-
match B signal and the settings of the OS3 and OS2 bits in TCSR. TCORB is initialized to H'FF.
Rev.2.00 May. 28, 2009 Page 282 of 732
REJ09B0059-0200
Timer Counter (TCNT)
Time Constant Register A (TCORA)
Time Constant Register B (TCORB)