DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 559

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The operation timings in slave transmit mode
are shown in figures 17.9 and 17.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to
4. Clear TRS for the end processing, and read ICDRR (dummy read). Then, SCL is free.
5. Clear TDRE.
(master output)
(master output)
(slave output)
processing
ICCRA to 1 (initial setting). Set the MST and TRS bits in ICCRA to select slave receive mode,
and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR
are set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission can be performed by writing transmit data to ICDRT every time TDRE is set.
1, with TDRE = 1. When TEND is set, clear TEND.
SCL
ICDRS
ICDRR
SDA
SDA
RDRF
RCVD
User
Slave Transmit Operation
Data n-1
Figure 17.8 Operation Timing in Master Receive Mode (2)
A
[5] Read ICDRR after setting RCVD
9
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
[7] Read ICDRR and clear RCVD
5
Bit 2
6
Rev.2.00 May. 28, 2009 Page 519 of 732
Bit 1
7
Section 17 I
Bit 0
Data n
8
A/
9
Data n
[6] Issue stop
2
condition
C Bus Interface 3 (IIC3)
REJ09B0059-0200
[8] Set slave
receive mode