DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 624

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• R0L is a return value of FPFR.
• Since the stack area is used in the initialization program, 128-byte stack area at the maximum
• Interrupts can be accepted during the execution of the initialization program. The program
8. Check the return value in the initialization program, FPFR (general register R0L)
9. Disable all interrupts and the use of a bus master other than the CPU
10. Set FKEY to H'5A to enable the user MAT programming.
11. Set the parameter which is required for programming
• Example of the FMPAR setting
• Example of the FMPDR setting
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REJ09B0059-0200
must be saved in RAM.
storage area and stack area in the on-chip RAM and register values must not be destroyed.
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time and the
voltage is applied for more than the specified time, flash memory may be damaged. Therefore,
interrupts and bus mastership moved to other than the CPU must be disabled.
When interrupts are disabled, bit 7 (I) in the condition code register (CCR) of the CPU should
be set to B'1 in interrupt control mode 0 or bits 7 and 6 (I and UI) in CCR should be set to B′11
in interrupt control mode 2. Then interrupts other than the NMI are retained and are not
executed.
The NMI interrupt must be masked within the user system.
The interrupts that are retained must be executed after all program processing.
The start address of the programming destination of the user MAT (FMPAR) is set to the
general register ER1. The start address of the program data area (FMPDR) is set to the general
register ER0.
FMPAR specifies the programming destination address. When an address other than one in the
user MAT area is specified, even if the programming program is executed, programming is not
executed and an error is returned to the return value parameter FPFR. Since the unit is 128
bytes, the lower eight bits of the address must be H'00 or H'80 as the boundary of 128 bytes.
When the storage destination of program data is flash memory, even if the program execution
routine is executed, programming is not executed and an error is returned to FPFR. In this
case, the program data must be transferred to the on-chip RAM and then programming must be
executed.