DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 543

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.2
ICCRB issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
a reset in IIC control.
Bit Bit Name
7
6
5
4
3
2
1
BBSY
SCP
SDAO
⎯
SCLO
⎯
IICRST
I
2
C Bus Control Register B (ICCRB)
Initial Value R/W
0
1
1
1
1
1
0
R/W
R/W
R
R/W
R
⎯
R/W
Description
Bus Busy
There are two functions: a flag function which indicates
whether the I
which issues start and stop conditions in master mode.
This bit is set to 1 when the SDA level changes from high
to low under the condition of SCL = high, assuming that the
start condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop condition
has been issued. Write 1 to BBSY and 0 to SCP to issue a
start condition. Also follow this procedure when re-
transmitting a start condition. Write 0 to BBSY and 0 to
SCP to issue a stop condition. To issue a start/stop
condition, use the MOV instruction.
Start/Stop Condition Prohibit
Controls the issue of start/stop conditions in master mode.
To issue a start condition, write 1 to BBSY and 0 to SCP.
Also follow this procedure when retransmitting a start
condition. To issue a stop condition, write 0 to BBSY and 0
to SCP. This bit is always read as 1. Even if 1 is written to
this bit, the data is not stored.
Monitors the SDA output level. When reading and the
SDAO bit is 1, the SDA pin outputs high. When reading
and the SDAO bit is 0, the SDA pin outputs low.
Reserved
The write value should always be 1.
Monitors the SCL output level. When reading and the
SCLO bit is 1, the SCL pin outputs high. When reading and
the SCLO bit is 0, the SCL pin outputs low.
Reserved
This bit is always read as 1.
Resets control parts except for I
to 1 when a hang-up occurred because of communication
failure during I
without setting ports and initializing registers.
IIC Control Part Reset
2
C bus is occupied or released and a function
2
C operation, I
Rev.2.00 May. 28, 2009 Page 503 of 732
Section 17 I
2
C control parts can be reset
2
C registers. If this bit is set
2
C Bus Interface 3 (IIC3)
REJ09B0059-0200