DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 139

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4
6.4.1
The external address space bus specifications consist of three elements: bus width, number of
access states, and the number of wait modes and program wait states. The bus width and number
of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the
bus controller.
Normal Extended Mode:
1. Bus Width
2. Number of Access States
3. Wait Mode and Number of Program Wait States
Table 6.2
Address Range
H'080000 to H'FBFFFF (15 Mbytes)
H'FC0000 to H'FCFFFF (64 kbytes)
H'FD0000 to H'FDFFFF (64 kbytes)
H'FE0000 to H'FEFFFF (64 kbytes)
H'FF0000 to H'FF9FFF (40 kbytes)
A bus width of 8 or 16 bits can be selected with the ABWn bit in BCRAn.
The number of access states for data access , 2-state or 3-state can be selected with the ASTn
bit in BCRAn. When 2-state access space is designated, wait state insertion is disabled.
When 3-state access space is designated by the ASTn bit in BCRAn, the number of program
wait states to be inserted automatically is selected with WMSn1, WMSn0, WCn1, and WCn0
in the BCRAn. From 0 to 3 program wait states can be selected.
The external extended wait function is effective when the low-speed device is connected to the
external address area.
For details on normal extended address range, external address area, as well as bus interface
specifications, refer to tables 6.2 and 6.3.
Bus Control
Bus Specifications
Address Range and External Address Area (Normal Extended Mode)
Area
Basic area (shares bus specification with area 1)
Area 1
Area 2
Area 3
Integrated with basic area when RAME = 0
Rev.2.00 May. 28, 2009 Page 99 of 732
REJ09B0059-0200