DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 578

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
18.4.1
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
18.4.2
In scan mode, A/D conversion is to be performed sequentially on the specified channels:
maximum four channels or maximum eight channels. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by software, TPU, or external trigger input, A/D
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
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external trigger input.
register to the channel.
this time, an ADI interrupt request is generated.
conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion
stops and the A/D converter enters the wait state.
conversion starts on the first channel in the specified channel set.
The consecutive A/D conversion on maximum four channels (SCANE = 1 and SCANS = 0) or
on maximum eight channels (SCANE = 1 and SCANS = 1) can be selected. When the
consecutive A/D conversion is performed on the four channels, the A/D conversion starts on
AN0 when CH3 = 0 and CH2 = 0, AN4 when CH3 = 0 and CH2 = 1, AN8 when CH3 = 1 and
CH2 = 0, or AN12 when CH3 = 1 and CH2 = 1. When the consecutive A/D conversion is
performed on the eight channels, the A/D conversion starts on AN0 when CH3 = 0 and CH2 =
0 and on AN8 when CH3 = 1 and CH2 = 0.
the corresponding A/D data register to each channel.
Operation
Single Mode
Scan Mode