DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 278
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 278 of 776
- Download datasheet (5Mb)
9.3.3
DACR enables the PWM outputs, and selects the output phase and operating speed.
Rev.2.00 May. 28, 2009 Page 238 of 732
REJ09B0059-0200
Bit
7
6
5
4
3
2
1
0
Bit Name
⎯
PWME
⎯
⎯
OEB
OEA
OS
CKS
PWMX (D/A) Control Register (DACR)
Initial Value
0
0
1
1
0
0
0
0
R/W
R/(W) Reserved
R/W
⎯
⎯
R/W
R/W
R/W
R/W
Description
The initial value should not be changed.
PWMX Enable
Starts or stops DACNT.
0: DACNT operates as a 14-bit up-counter
1: DACNT halts at H'0003
Reserved
These bits are always read as 1 and cannot be
modified.
Output Enable B
Enables or disables output on PWMX (D/A) channel B.
0: PWMX (D/A) channel B output (at the PWX1 output
1: PWMX (D/A) channel B output (at the PWX1 output
Output Enable A
Enables or disables output on PWMX (D/A) channel A.
0: PWMX (D/A) channel A output (at the PWX0 output
1: PWMX (D/A) channel A output (at the PWX0 output
Output Select
Selects the phase of the PWMX (D/A) output.
0: Direct PWMX (D/A) output
1: Inverted PWMX (D/A) output
Clock Select
Selects the PWMX (D/A) resolution. Eight kinds of
resolution can be selected.
0: Operates at resolution (T) = system clock cycle time
1: Operates at resolution (T) = system clock cycle time
pin) is disabled
pin) is enabled
pin) is disabled
pin) is enabled
(t
(t
× 16384.
cyc
cyc
)
) × 2, × 64, × 128, × 256, × 1024, × 4096, and
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