DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 606

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 20.4 Parameters and Target Modes
Note:
(1) Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the 2-kbyte area starting from the address specified by FTDAR.
Download control is set by the programming/erasing interface registers, and DPFR indicates the
return value.
(a) Download Pass/Fail Result Parameter (DPFR: Single Byte of On-Chip RAM Start Address
DPFR indicates the return value of the download result. The value of this parameter can be used to
determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to
1 is difficult, the certain determination must be performed by setting the single byte of the start
address specified by FTDAR to the value other than the return value of download (for example,
H'FF) before the download start (before setting the SCO bit to 1).
Rev.2.00 May. 28, 2009 Page 566 of 732
REJ09B0059-0200
Name of
Parameter
Download
pass/fail result
Flash pass/fail
result
Flash
programming/
erasing frequency
control
Flash multi-
purpose address
area
Flash multi-
purpose data
destination area
Flash erase block
select
Specified by FTDAR)
* A single byte of the start address to download an on-chip program, which is specified by
FTDAR
Abbrevia-
tion
DPFR
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
Down-
load
⎯
⎯
⎯
⎯
⎯
Initializa-
tion
⎯
⎯
⎯
⎯
Program-
ming
⎯
⎯
⎯
Erasure
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Alloca-
tion
On-chip
RAM*
R0L of
CPU
ER0 of
CPU
ER1 of
CPU
ER0 of
CPU
R0L of
CPU