DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 507

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4.5
Figure 16.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
Figure 16.7 shows a sample flowchart for transmission in asynchronous mode.
Figure 16.6 Example of Operation in Transmission in Asynchronous Mode (Example with
written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty (TXI) interrupt
request is generated. If the TXI interrupt routine writes the next transmit data to TDR before
transmission of the current transmit data has finished, continuous transmission can be enabled.
multiprocessor bit (may be omitted depending on the format), and stop bit.
sent, and then serial transmission of the next frame is started.
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
TXI interrupt
request generated
TDRE
TEND
Serial Data Transmission (Asynchronous Mode)
1
Start
bit
0
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt processing routine
D0
D1
1 frame
Data
8-Bit Data, Parity, One Stop Bit)
D7
Parity
bit
0/1
TXI interrupt
request generated
Stop
bit
1
Start
bit
0
D0
D1
Rev.2.00 May. 28, 2009 Page 467 of 732
Data
D7
Parity
bit
TEI interrupt
request generated
0/1
Stop
bit
1
REJ09B0059-0200
Idle state
(mark state)
1