DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 355
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Timer general register B_2 (TGRB_2)
Common Registers:
• Timer start register (TSTR)
• Timer synchro register (TSYR)
12.3.1
TCR controls the TCNT operation for each channel. The TPU has a total of three TCR registers,
one for each channel (channels 0 to 2). TCR settings should be made only when TCNT operation
is stopped.
Bit
7
6
5
4
3
2
1
0
Bit Name Initial Value
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 2 to 0
Select the TCNT counter clearing source. See tables 12.3
and 12.4 for details.
Clock Edge 1, 0
Select the input clock edge. When the internal clock is
counted using both edges, the input clock cycle is 1/2
(example: φ/4 both edges = φ/2 rising edge). If phase
counting mode is used on channels 1 and 2, this setting
is ignored and the phase counting mode setting has
priority. Internal clock edge selection is valid when the
input clock is φ/4 or slower. This setting is ignored if the
input clock is φ/1 and the rising edge counting is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
[Legend] x: Don't care
Timer Prescaler 2 to 0
Select the TCNT counter clock. The clock source can be
selected independently for each channel. See tables 12.5
to 12.7 for details.
Rev.2.00 May. 28, 2009 Page 315 of 732
REJ09B0059-0200
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