DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 537
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 537 of 776
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This LSI has a four-channel I
The I
interface functions. The register configuration that controls the I
Philips configuration, however.
Figure 17.1 shows a block diagram of the I
Figure 17.2 shows an example of I/O pin connections to external circuits.
17.1
• Continuous transmission/reception
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Multiple slave addresses can be set
• Six interrupt sources
• Direct bus drive
IFIIC50A_010020030300
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of the SCL is monitored per bit, and the timing is synchronized
automatically
If transfer is not ready, set the SCL to low until preparations are completed.
Maximum three types of slave addresses can be set independently. Using the slave address
mask register enables more slave addresses to be set.
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
SCL and SDA pins function as NMOS open-drain outputs.
2
C bus interface conforms to and provides a subset of the Philips I
Features
Section 17 I
2
C bus interface 3 (IIC3).
2
C Bus Interface 3 (IIC3)
2
C bus interface 3.
Rev.2.00 May. 28, 2009 Page 497 of 732
2
C bus differs partly from the
Section 17 I
2
C bus (inter-IC bus)
2
C Bus Interface 3 (IIC3)
REJ09B0059-0200
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