DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 530

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.8
16.8.1
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, see section 22, Power-Down Modes.
16.8.2
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set,
and the PER flag may also be set. Note that, since the SCI continues the receive operation even
after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
16.8.3
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output)
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark
state (high level) or send a break during serial data transmission. To maintain the communication
line at mark state until the TE bit is set to 1, set both DDR and DR to 1. Since the TE bit is cleared
to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a
break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission
state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
16.8.4
Transmission cannot be started when a receive error flag (ORER, FER, or PER) in SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note that the receive error flags cannot be cleared to 0 even if the RE bit in
SCR is cleared to 0.
16.8.5
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new
data is written to TDR while the TDRE flag is 0, the previous data in TDR is lost because the
previous data has not been transferred to TSR yet. Be sure to write transmit data to TDR after
confirming that the TDRE flag is set to 1.
Rev.2.00 May. 28, 2009 Page 490 of 732
REJ09B0059-0200
Usage Notes
Module Stop Mode Setting
Break Detection and Processing
Mark State and Break Sending
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Relation between Writing to TDR and TDRE Flag