DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 600

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 May. 28, 2009 Page 560 of 732
REJ09B0059-0200
Bit
3
2, 1
0
Bit Name
WEINTE
⎯
SCO
Initial
Value
0
All 0
0
R/W
R/W
R/W
(R)/W*
Description
Program/Erase Enable
Modifies the space for the interrupt vector table, when
interrupt vector data is not read successfully during
programming/erasing flash memory or switching
between a user MAT and a user boot MAT. When this bit
is set to 1, interrupt vector data is read from address
spaces H'FF6000 to H'FF607F (on-chip RAM space),
instead of from address spaces H'000000 to H'00007F
(up to vector number 31). Therefore, make sure to set
the vector table in the on-chip RAM space before setting
this bit to 1.
The interrupt exception handling on and after vector
number 32 should not be used because the correct
vector is not read, resulting in the CPU runaway.
0: The space for the interrupt vector table is not
1: The space for the interrupt vector table is modified.
Reserved
The initial value should not be changed.
Source Program Copy Operation
Requests the on-chip programming/erasing program to
be downloaded to the on-chip RAM. When this bit is set
to 1, the on-chip program which is selected by
FPCS/FECS is automatically downloaded in the on-chip
RAM specified by FTDAR. In order to set this bit to 1,
H'A5 must be written to FKEY and this operation must
be executed in the on-chip RAM.
Four NOP instructions must be executed immediately
after setting this bit to 1. Since this bit is cleared to 0
when download is completed, this bit cannot be read as
1. All interrupts must be disabled during download. This
should be made in the user system.
0: Download of the on-chip programming/erasing
program to the on-chip RAM is not executed.
modified.
When interrupt vector data is not read successfully,
the operation for the interrupt exception handling
cannot be guaranteed. An occurrence of any
interrupts should be masked.
Even when interrupt vector data is not read
successfully, the interrupt exception handling up to
vector number 31 is enabled.