S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 909

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

25.3.2.7
The FSTAT register reports the operational status of the Flash module.
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Freescale Semiconductor
ERSVIE1
ERSVIE0
Offset Module Base + 0x0006
DFDIE
Reset
SFDIE
Field
3
2
1
0
W
R
CCIF
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
1 An interrupt will be requested whenever the SFDIF flag is set (see
Flash Status Register (FSTAT)
1
7
= Unimplemented or Reserved
Table 25-16. FERCNFG Field Descriptions (continued)
0
0
6
Figure 25-11. Flash Status Register (FSTAT)
MC9S12XE-Family Reference Manual Rev. 1.24
ACCERR
0
5
FPVIOL
0
4
Description
MGBUSY
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1)
0
3
Section
Section
Section
Section
Section
RSVD
25.3.2.8)
0
2
25.3.2.8)
25.3.2.8)
25.3.2.8)
25.3.2.8)
0
1
(1)
MGSTAT[1:0]
Section
0
0
1
25.6).
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