S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 378

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

Chapter 10 XGATE (S12XGATEV3)

Upon detecting an error condition caused by erratic application code, the XGATE module will

immediately terminate program execution and trigger a non-maskable interrupt to the S12X_CPU. There

are three error conditions:

All opcodes which are not listed in section

opcode fetches as well as illegal load and store accesses are deﬁned on chip level. Refer to the

S12X_MMC Section for a detailed information.

Execution of an illegal opcode

Illegal opcode fetches

Illegal load or store accesses

Software Error Detection

When executing a branch (BCC, BCS,...), a jump (JAL) or an RTS

instruction, the XGATE prefetches and discards the opcode of the following

instruction. The XGATE will perform its software error handling actions

(see above) if this opcode fetch is illegal.

Figure 10-25. Algorithm for Locking and Releasing Semaphores

1 ⇒ XGSEM[n]

0 ⇒ XGSEM[n]

MC9S12XE-Family Reference Manual Rev. 1.24

Section 10.8, “Instruction Set”

are illegal opcodes. Illegal

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