S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 258

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S912XEQ384J3MALR

Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
Chapter 5 External Bus Interface (S12XEBIV4)
state operation (stretching) of the external bus access is done in emulation modes when accessing internal
memory or emulation memory addresses.
In both modes observation of the internal operation is supported through the external bus (internal
visibility).
5.5.2.1
This mode is used for emulation systems in which the target application is operating in normal single-chip
mode.
Figure 5-5
The timing diagram for this operation is shown in:
The associated timing numbers are given in:
Timing considerations:
258
Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’
Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAIT disabled)’
Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing.
LSTRB has the same timing as RW.
shows the PRU connection with the available external bus signals in an emulator application.
Example 2a: Emulation Single-Chip Mode
ADDR[22:20]/ACC[2:0]
Figure 5-5. Application in Emulation Single-Chip Mode
ADDR[22:0]/IVD[15:0]
S12X_EBI
MC9S12XE-Family Reference Manual Rev. 1.24
ADDR[19:16]/
IQSTAT[3:0]
DATA[15:0]
ECLKX2
LSTRB
ECLK
RW
EMULMEM
PRU
Emulator
PRR
Ports
Freescale Semiconductor

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