S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 566

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S912XEQ384J3MALR

Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Read: Anytime
Write: Has no effect.
All bits reset to zero.
These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding
IOSx bits in TIOS should be cleared (see
14.4
This section provides a complete functional description of the ECT block, detailing the operation of the
design from the end user perspective in a number of subsections.
566
Module Base + 0x003D
Module Base + 0x003E
Module Base + 0x003F
Reset
Reset
Reset
W
W
W
R
R
R
Functional Description
TC15
TC7
TC7
15
0
0
0
7
7
Figure 14-65. Timer Input Capture Holding Register 3 High (TC3H)
Figure 14-64. Timer Input Capture Holding Register 2 Low (TC2H)
Figure 14-66. Timer Input Capture Holding Register 3 Low (TC3H)
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
TC14
TC6
TC6
14
0
0
0
6
6
MC9S12XE-Family Reference Manual Rev. 1.24
TC13
TC5
TC5
13
0
0
0
5
5
Section 14.4.1.1, “IC
TC12
TC4
TC4
12
0
0
0
4
4
TC11
TC3
TC3
11
0
0
0
3
3
Channels”).
TC10
TC2
TC2
10
0
0
0
2
2
Freescale Semiconductor
TC1
TC9
TC1
0
0
0
1
9
1
TC0
TC8
TC0
0
0
0
0
8
0

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