S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 496

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles
(External Reset), the internal reset remains asserted longer.
11.5.1.1
The S12XECRG generates a Clock Monitor Reset in case all of the following conditions are true:
The reset event asynchronously forces the configuration registers to their default settings. In detail the
CME and the SCME are reset to logical ‘1’ (which changes the state of the SCME bit. As a consequence
the S12XECRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel the
clock quality check starts. As soon as clock quality check indicates a valid Oscillator Clock the
S12XECRG switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running
in parallel to the reset generator, the S12XECRG may leave Self Clock Mode while still completing the
internal reset sequence.
11.5.1.2
When COP is enabled, the S12XECRG expects sequential write of $55 and $AA (in this order) to the
ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts.
If the program fails to do this the S12XECRG will generate a reset.
11.5.1.3
The on-chip voltage regulator detects when V
on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the
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Clock monitor is enabled (CME = 1)
Loss of clock is detected
Self-Clock Mode is disabled (SCME = 0).
Clock Monitor Reset
Computer Operating Properly Watchdog (COP) Reset
Power On Reset, Low Voltage Reset
SYSCLK
RESET
MC9S12XE-Family Reference Manual Rev. 1.24
possibly
SYSCLK
not
running
Figure 11-21. RESET Timing
ICRG drives RESET pin low
) (
DD
128+n cycles
to the MCU has reached a certain level and asserts power
with n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
) (
)
(
RESET pin
released
64 cycles
)
(
possibly
RESET
driven low
externally
)
(
Freescale Semiconductor